Supero X7SBA, User Manual

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X7SBA User's Manual
Compatible FPU Code
(Available when supported by the CPU.)
Set to Enabled to keep the content of the last instruction Operating Code (OP
Code) in the fl oating point (FP) state. The options are Disabled and Enabled.
L3 Cache
(Available when supported by the CPU.)
Set to Enabled to enable the function of L3 Cache to optimize system and CPU
performance. The options are Disabled and Enabled .
Thermal Management 2
(Available when supported by the CPU.)
Set to Enabled to use Thermal Management 2 (TM2) which will lower CPU voltage
and frequency when the CPU temperature reaches a predefi ned overheat threshold.
Set to Disabled to use Thermal Manager 1 (TM1), allowing CPU clocking to be
regulated via CPU Internal Clock modulation when the CPU temperature reaches
the overheat threshold.
Adjacent Cache Line Prefetch
(Available when supported by the CPU.)
The CPU fetches the cache line for 64 bytes if this option is set to Disabled. The
CPU fetches both cache lines for 128 bytes as comprised if Enabled. The options
are Disabled and Enabled .
Set Maximum Ext. CPUID=3
When set to Enabled, the Maximum Extended CPUID will be set to 3. The options
are Disabled and Enabled.
Echo TPR
Set to Enabled to prevent xTPR messages from being sent to the system. The
options are Disabled and Enabled .
C1 Enhanced Mode
(Available when supported by the CPU.)
Set to Enabled to enable Enhanced Halt State to lower CPU voltage/frequency to
prevent overheat. The options are Enabled and Disabled . Note: please refer to
Intel’s web site for detailed information.
Intel <R> Virtualization Technology
(Available when supported by the
CPU.)
Select Enabled to use the feature of Virtualization Technology to allow one platform
to run multiple operating systems and applications in independent partitions,
creating multiple "virtual" systems in one physical computer. The options are
Enabled and Disabled .
Note : If there is any change to this setting, you will need to power off and restart
the system for the change to take effect. Please refer to Intel’s web site for detailed
information.