Supero X7SBA, User Manual

Page: 15 / 126

Chapter 1: Introduction
1-9
1-2 Chipset Overview
The Intel 3210 chipset, designed for use with the Quad Core/Dual Core Intel® Xeon
3000 Series Processor, is comprised of two primary components: the Memory
Controller Hub (MCH) and the I/O Controller Hub ICH9R. In addition, the PXH-V
chip is used for added functionality. The X7SBA provides the performance and
feature-set required for cost-effective, power-effi cient UP system platforms.
Memory Controller Hub (MCH)
The function of the MCH is to manage the data fl ow between four interfaces: the
CPU interface, the DDR2 System Memory Interface, the PCI Express Interface,
and the Direct Media Interface (DMI).
The MCH is optimized for a Quad Core/Dual Core Xeon 3000 series processor
in the LGA775 Land Grid Array Package with a FSB frequency of 1333/1066/800
MHz. The 3210 MCH supports 36-bit host bus addressing, allowing the CPU to
access to the entire 64 GB of the host address space. It also has a 12-deep In-
Order Queue to support up to 12 outstanding pipelined address request on the host
bus. It supports one or two channels of DDR2 SDRAM. The 3210 platform uses
the ninth generation I/O Controller Hub (ICH9R) to provide I/O related functions.
The Ninth Generation I/O Controller Hub (ICH9R)
The I/O Controller ICH9R provides the data buffering and interface arbitration
required for the system to operate effi ciently. It also provides the bandwidth needed
for the system to maintain its peak performance. The Direct Media Interface (DMI)
provides the connection between the MCH and the ICH9R. The ICH9R supports
up to two PCI-Express x8 slots, six Serial ATA ports and eight USB 2.0 ports. In
addition, the ICH9R offers the Intel Matrix Storage Technology which provides vari-
ous RAID options for data protection and rapid data access. It also supports the
next generation of client management through the use of PROActive technology
in conjunction with Intel's next generation Gigabit Ethernet controller.
Intel ICH9R System Features
The I/O Controller Hub provides the I/O subsystem with access to the rest of the
system. Functions and capabilities include:
Advanced Power Management
SMBus 2.0 (I
2
C)
SST/PECI Fan Speed Control
SPI Flash
Low Pin Count (LPC) Interface