Supero SUPER S2DM3, User Manual

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Chapter 1: Introduction
1-13
Introduction
1-2 Chipset Overview
Intel’s 840 chipset is based on the new modular design introduced by the
800 series chipsets and consisting of three main components. The 82840
Memory Controller Hub (MCH) provides support for AGP2x/4x and AGP Pro.
An 82801 I/O Controller Hub (ICH) connects the PCI slots, IDE controllers
and USB ports to the MCH via an accelerated hub architecture. The third
main component is the 82802 Firmware Hub (FWH), which stores both sys-
tem and video BIOS and includes a Random Number Generator (RNG).
Memory Controller Hub (MCH)
The MCH includes the host (CPU) interface, DRAM interface, ICH interface,
4xAGP interface and P64 interface for the 840 chipset. It contains ad-
vanced power management logic and supports dual channels for DRAM.
The AGP 2.0 interface supports 4x data transfer and 2x/4x fast write capa-
bility and operates at a peak bandwidth of 266 MB/sec. The MCH host
interface bus runs at 133/100 MHz.
I/O Controller Hub (ICH)
The ICH is the Controller Hub for the I/O subsystem and integrates many of
the Input/Output functions of the 840 chipset, including a two-channel
UDMA/66 Bus Master IDE controller. It also provides the interface to the PCI
Bus and communicates with the MCH over a dedicated hub interface.
Firmware Hub (FWH)
The FWH is a component that brings added security and manageability to
the PC platform infrastructure. This device includes an integrated Random
Number Generator (RNG) for stronger encryption, digital signing and secu-
rity protocols. The FWH stores the system BIOS and video BIOS to eliminate
a redundant nonvolatile memory component.
PCI 64-bit Hub (P64H)
The P64H chip provides a bridge between the MCH and the PCI Bus. It has
a 16-bit primary hub interface to the MCH and a secondary 64-bit PCI Bus
interface, which supports both 64-bit and 32-bit PCI devices. The P64H is
PCI 2.2 compliant.