Supero PDSBM-LN1, User Manual

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PDSBM-LN1/PDSBM-LN2/PDSBM-LN2+ User's Manual
written into L1, L2, L3 cache inside the CPU to speed up CPU operations. Select
Uncached to disable this function. Select Write Through to allow data to be cached
into the buffer and written into the system memory at the same time. Select Write
Protect to prevent data from being written into the extended memory area above 1
MB. Select Write Back to allow the CPU to write data back directly from the buffer
without writing data to the System Memory to optimize CPU operation. The options
are Uncached, Write Through, Write Protect, and Write Back .
Discrete MTRR Allocation
If enabled, MTRRs (-Memory Type Range Registers) are confi gured as distinct,
separate units and cannot be overlapped. If enabled, the user can achieve better
graphic effects when using a Linux graphic driver that requires write-combining
confi guration with 4GB or more memory. The options are Enabled and Disabled.
X
PCI Confi guration
Access the submenu to make changes to the following settings for PCI devices.
X
Onboard PCI-Exp. x1 GNIC1
Access the submenu for each of the settings above to make changes to the
following:
PCI Express Port#5 GNIC1
Select Enabled to always enable PCI-Ex1 Port#5 GNIC1. Select Disabled to
disable Port#5 GNIC1. The options are Auto , Enabled and Disabled.
Option ROM Scan
When enabled, this setting will initialize the device expansion ROM. The options
are Enabled and Disabled.
Enable Master
This setting allows you to enable the device specifi ed as the PCI bus master.
The options are Enabled and Disabled.
Latency Timer
This setting allows you to set the clock rate for the Bus Master. A high-priority,
high-throughout device may benefi t from a greater clock rate. The options are
Default , 0020h, 0040h, 0060h, 0080h, 00A0h, 00C0h, and 00E0h. For Unix,
Novelle and other Operating Systems, please select the option: other. If a drive
fails after the installation of a new software, please change this setting and try
again. A different OS requires a different Bus Master clock rate .