Chapter 1: Introduction
1-9
1-2 Chipset
Overview
The Intel 82946GZ chipset, designed for use with the Intel Xeon 3000 Series/Core 2
Duo processor and Pentium D/Pentium 4 Processor in desktop platforms, contains
two components: GMCH (North Bridge) and ICH7R (South Bridge). The GMCH is
used for the host bridge, and the ICH7R, for the I/O subsystems.
Graphics Memory Controller Hub (GMCH)
The GMCH manages the data fl ow between its four interfaces: the processor
interface (FSB), the system memory interface (DRAM controller), the integrated
graphics interface, the External Graphics interface, and the I/O Controller through
DMI interface. It provides bus arbitration between the four interfaces when each
initiates transactions. The processor interface supports the Pentium 4 subset of
the Extended Mode of the Scalable Bus Protocol. The GMCH supports a 64-byte
Cache Line, 36-bit host addressing, decoding up to 4 GB of the CPU's memory
address space, allowing the processor to access the entire 4 GB of the GMCH's
memory address space. The GMCH also supports one or two channels of SDRAM
and the PCI Express-based graphics attached devices.
The Intel 946GZ platform supports the seventh generation I/O Controller Hub (Intel
ICH7R) to provide a multitude of I/O related features. The Direct Media Interface
(DMI) provides the chip-to-chip connection between the GMCH and the ICH7R.
Intel I/O Controller Hub 7R (ICH7R)
The I/O Controller (ICH7R) provides the data buffering and interface arbitration
required for the system to operate effi ciently. It also provides the bandwidth needed
for the system to maintain its peak performance. The ICH7R supports PCI slots,
Serial ATA ports, USB 2.0 ports and dual channel IDE devices.
Intel ICH7R System Features
The I/O Controller Hub provides the I/O subsystem with access to the rest of the
system. The ICH7R supports the following:
*Serial ATA (SATA) Controller with HostRAID support
*Advanced Confi guration and Power Interface, Version 2.0 (ACPI)
*Advanced Host Controller Interface (AHCI)
*Low Pin Count (LPC) Interface
*Serial Peripheral Interface (SPI)
*Compatibility Modules (DMA Controller, Timer/Counter, Interrupt Controller)
Summary of Contents for PDSBM-LN1
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