Chapter 4: BIOS
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Enable Pcode WA (Workaround) for SAI (Security Attribute of the Initiator) PG
(Policy Group)
Pcode, a register transfer language designed for reverse engineering, translates individual
processor instructions into a sequence of Pcode operations in order to facilitate the
construction of data-flow graphs and dissembling of processor instructions for machine
application. Select Enabled to allow Pcode to work around the SAI group policy to achieve
a solution with a next-step instruction. The options are
Disabled
and Enabled.
Mirror Mode (Unavailable when "ADDDC Sparing" below is set to Disabled)
Use this feature to configure the mirror mode settings for all 1LM/2LM memory modules
in the system which will create a duplicate copy of data stored in the memory to increase
memory security, but it will reduce the memory capacity into half. The options are
Disabled
,
Full Mirror Mode, and Partial Mirror Mode.
UEFI ARM Mirror
If this feature is set to Enable, mirror mode configuration setting for UEFI-based Address
Range memory will be enabled upon system boot. This will create a duplicate copy of data
stored in the memory to increase memory security, but it will reduce the memory capacity
into half. The options are
Disable
and Enabled.
Correctable Error Threshold
Use this feature to enter the threshold value for correctable memory errors. The default
setting is
512
.
Partial Cache Line Sparing (PCLS)
Select Enabled to support partial cache line sparing, which will allow partial of data
contained in a cache line to be copied in the cache memory for safe-keeping/data security.
The options are Disabled and
Enabled
.
ADDDC (Adaptive Double Device Data Correction) Sparing
Select Enable for Adaptive Double Device Data Correction (ADDDC) support, which will
not only provide memory error checking and correction but will also prevent the system
from issuing a performance penalty before a device fails. Please note that virtual lockstep
mode will only start to work for ADDDC after a faulty DRAM module is spared. The options
are Disabled and
Enabled
.
Patrol Scrub
Patrol Scrubbing is a process that allows the CPU to correct correctable memory errors
detected in a memory module and send the corrections to the requestor (the original source).
When this feature is set to Enable, the IO hub will read and write back one cache line every
16K cycles if there is no delay caused by internal processing. By using this method, roughly
64 GB of memory behind the IO hub will be scrubbed every day. The options are Disabled
Enabled, Disabled, and
Enable at End of POST (Power_On Self Test)
.
