Sun Microsystems Netra T4 AC100, Service And System Reference Manual

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Chapter 10 Functional Description 10-7
The main memory is implemented with x144 DIMMs, also referred to as NG-DIMMs
(Next Generation Dual-Inline Memory Modules). The system supports up to eight
installed NG-DIMMs.
Note –
The memory bus is clocked at half the system frequency through a clock
connected directly to the CPU module.
The DIMMs also support a SEEPROM for identifying and configuring subsystem
memory.
The CPU module memory controller performs reads and writes in blocks of 64 bytes.
On non cacheable reads the extraneous data is dropped. On non cacheable write, the
processor must perform a read-modify-write. The memory space is cached.
The memory subsystem supports 2- and 4-way logical interleaving. The unit of
interleaving is a logical bank. A group of four DIMMs corresponds to two logical
banks for interleaving purposes. The interleaving is based on multiples of 64 bytes.
Main memory interleaving is described in more details in Section 10.2.2.3,
“Interleaving” on page 10-10.