Stanford Research Systems DS335, User Manual

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5-2 Circuitry
DS335 Synthesized Function Generator
There is a TCXO option for the 10 MHz clock. When present, the TCXO may be tuned to exactly 10 MHz. The
frequency is calibrated by altering the constant used to compute the PIR value for the ASIC phase
accumulator.
The buffered 10 MHz is divided by two by a D-type flip-flop (74HC74, U101A) to provide a 5 MHz clock to the
CPU. A second flip-flop (U101B) divides the 5 MHz by two to provide a 2.5 MHz clock to the 8253
counter/timer, and to the UART and GPIB controller on the communications interface board.
The 8253 provides three additional clocks by dividing its 2.5 MHz input: a 500 Hz RTI is generated by dividing
by 5000, a 1 kHz tone for the speaker is generated by dividing by 2500, and a 16x clock for 9600 baud is
generated by dividing by 16 (which will have a 1.7% error).
Communications Interface Header
An 18 pin header to the optional GPIB/RS232 interface is shown on sheet DS335FP. The computer interface
must be ground referenced, while the function generator (and so its CPU, etc.) must float. To accommodate
this, communications between the CPU and the interface are done serially, via opto-isolators. Data and
commands are shifted to and from the interface with the port-strobe "DATA_CLK". Commands are executed
(a register read, for example) when the port strobe "-CMD_STB" is asserted.
A separate, ground referenced power supply is generated on the interface PCB by rectifying and regulating
the 9 Vac which is supplied to the header.
GPIB and RS232 interrupts can assert the maskable interrupt to the Z80. If no interface is present, this
interrupt will not be asserted. The CPU tests for the presence of the interface on power-up by shifting data
though the interface and looking for its return (with a 16 cycle delay, of course).
Data to the interface is buffered by a D-type flip-flop, (74HC74, U107A). The MSB of the data bus is clocked
into the flip-flop on the leading edge of the DATA_CLK, and clocked into the interface's shift register on the
trailing edge of the DATA_CLK. This is done to eliminate processor noise on the ribbon cable when there are
no communications. A byte is transferred to the interface with eight outputs and eight left-shift instructions.
Battery Back-up
The contents of the 32Kx8 CMOS RAM are preserved when the power is turned off by a Lithium battery. The
CS to the RAM is disabled on power down by the -RESET, which turns off the NPN transistor (Q101, a
2N3904).
Display Driver (DS335M2)
The front panel display is time multiplexed: two digits, and seven indicators may be refreshed, and six keys
read during each of four successive strobe periods.
To refresh a part of the front panel display, one STROBE column is pulled high by writing a zero to the
corresponding position in the LED_STB latch (U203, a 74HC374). For example, writing a zero to Q0 will
saturate the PNP transistor Q200, and pull STROBE_0 to +5 volts.
Digit segments and LED indicators within a particular STROBE column are turned on by writing a zero to the
corresponding position in the LED_EVEN, LED_ODD, or LED_LAMP latches (U200-201, 74HC374's). For
example, writing a zero to Q0 of the LED_EVEN latch will cause the 'a' segment of the 'even' digit display in
the selected strobe column to turn 'on'.
There is a watch-dog circuit (U111, D200, C200, and R229) which will turn off the front panel displays if the
processor stops refreshing the LED_STROBE latch. The circuit pumps charge onto C200 with every output to
the LED_STROBE latch. C200 is discharged by R229 if the port strobes cease, removing the output enable
from the 74HC374 display drivers.