Stanford Research Systems DS335, User Manual

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Introduction 2-1
DS335 Synthesized Function Generator
Introduction to Direct Digital Synthesis
Introduction Direct Digital Synthesis (DDS) is a method of generating very pure
waveforms with extraordinary frequency resolution, low frequency switching
time, crystal clock-like phase noise, and flexible sweeping capabilities. As an
introduction to DDS let's review how traditional function generators work.
Traditional Generators Frequency synthesized function generators typically use a phase-locked loop
(PLL) to lock an oscillator to a stable reference. Wave-shaping circuits are
used to produce the desired function. It is difficult to make a very high
resolution PLL so the frequency resolution is usually limited to about 1:10
6
(some sophisticated fractional-N PLLs do have much higher resolution). Due
to the action of the PLL loop filter, these synthesizers typically have poor
phase jitter and frequency switching response. In addition, a separate wave-
shaping circuit is needed for each type of waveform desired, and these often
produce large amounts of waveform distortion.
DDS DDS works by generating addresses to a waveform ROM to produce data for
a DAC. However, unlike earlier techniques, the clock is a fixed frequency
reference. Instead of using a counter to generate addresses, an adder is
used. On each clock cycle, the contents of a Phase Increment Register are
added to the contents of the Phase Accumulator. The Phase Accumulator
output is the address to the waveform ROM (see diagram below). By
changing the Phase Increment the number of clock cycles needed to step
through the entire waveform ROM changes, thus changing the output
frequency.
Frequency changes now can be accomplished phase continuously in only
one clock cycle. And the fixed clock eliminates phase jitter, requiring only a
simple fixed frequency anti-aliasing filter at the output.
The DS335 uses a custom Application Specific Integrated Circuit (ASIC) to
implement the address generation in a single component. The frequency
resolution is equal to the resolution with which the Phase Increment can be
set. In the DS335, the phase registers are 48 bits long, resulting in an
impressive 1:10
14
frequency resolution. The ASIC also contains a modulation
control CPU that operates on the Phase Accumulator, Phase Increment, and
external circuitry to allow digital synthesis and control of waveform sweeps.
The Modulation CPU uses data stored in the Modulation RAM to produce
frequency sweeps. All modulation parameters, such as rate, and frequency
deviation, are digitally programmed.
Figure 1:
Block diagram of SRS
DDS ASIC