Stanford Research Systems DS335, User Manual

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5-6 Circuitry
DS335 Synthesized Function Generator
Function Selection (DS335M6)
The DPDT relay (U603, an HS212) selects between the filtered (and perhaps attenuated) waveform DAC
output, and the output of the square wave generator. If the square wave output is not being used, then the
square wave amplitude will be set to zero (SW_AMPL=-5 Vdc) so as to reduce crosstalk in the function select
relay. The selected function is passed to the differential output amplifier.
Output Amplifier (DS335M7)
The output amplifier is a high speed, low distortion, discrete transistor differential amplifier. The gain is x-10
for the inverting input, and x12 for the non-inverting input, and the 3 dB bandwidth is 35 MHz, it has a phase
linear response to about 175 MHz, and a THD of about 0.05% to 50 kHz. The amplifier has a very low offset
drift, as its dc characteristics are stabilized by an external compensated op-amp.
The amplifier has a very symmetric design. This, together with it class A operation and high open loop
bandwidth, keeps it distortion very low. In this circuit description, only the 'top-half' will be described, as the
'bottom-half' of the amplifier operates in a completely symmetrical and complimentary manner.
The signal is applied to the input differential pair (Q701 and Q702, 2N5770's). The input pair run in a constant
current configuration, with the constant current source (Q706 with R741 and D701). The pnp transistor (Q700)
provides an ac current to absorb the feedback current from R705. Since the input differential pair runs at
constant current, independent of the input signal, their base-emitter voltages are constant, and so are not a
source of distortion.
To understand the operation of the amplifier, consider events when a positive input signal is applied. The
base of Q701 goes up, while Q702's base goes down. This increases Q701's collector current, pulling down
the base of the emitter follower, Q709, which pulls the base of Q710 and Q711 down, increasing their
collector currents. This current will cause the collector voltage of Q710 to slew very quickly, and with lots of
gain, because the collector load is a very high impedance. The Darlington pair, Q712 and Q713, buffer this
node to drive the output, which is a 100 Ohm load. The current imbalance at the high impedance node will
cause the output to continue to slew until the feedback current (though R703 and R747) brings the input
differential pair back into balance.
The ac gain is adjusted by setting R703. The ac gain is adjusted to match the dc gain (which is controlled by
the op-amp and its feedback resistor network.) The ac gain is determined by the ratio of the feedback
resistors to the emitter resistors.
The op-amp (U700, a CA3140) and its feedback resistors (R700,701,702 and R723) stabilize the dc
characteristics. The op-amp is externally compensated so that it will only correct low frequency errors, and so
will not affect high frequency performance. The output of U700 is buffered (for extra current drive) by U701A
and U701B.
Output Attenuator (DS335M8)
The output attenuator is a relay controlled, 50 Ohm attenuator, which allows attenuation in a binary sequence
of 2 dB steps. When the power is removed (or on RESET) all of the attenuators are switched 'in'. The relays
are controlled by bits written to the 8 bit latch, U800, a 74HC273. Outputs from the latch are buffered by npn
emitter followers (U801, a CA3082), which drive the relay coils. Each 2 dB attenuator can reduce the output
by a factor of 0.794. Output levels between these steps are obtained by adjusting the reference level to the
waveform DAC. The total attenuation is 30 dB, or a factor of 0.0316, which will reduce the 7.94 Vpp level from
the output amplifier to 0.25 Vpp. For ac levels below this, the pre-attenuator will be used (Sheet FG6) to
provide up to 14 dB additional attenuation (for levels down to 50 mVpp).