Spectrum Digital TMS320DM368, Technical Reference

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Spectrum Digital, Inc
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2.1.1.2.28 Register 725, CCD Internal I/O Read/Write Register 3
Register 725 is a 8 bit, read/write register that controls CPLD GPIO input on read, and
out value on write. The default data is 0b00000000. The table below shows the
mapping of these bits.
2.1.1.3 Key Pad Interface
The DM368 has an internal key pad controller. The key pad interface is multiplexed with
the address lines on the asynchronous EMIF. CBTLV multiplexers are used to redirect
the key pad interface to the key pad matrix. This interface can only be used when CE0
is in the NAND configuration. A control bit in the CPLD enables the Mux select on the
CBTLV multiplexers. The 16 bit switch key pad matrix is set up on a 4 x 4 matrix on the
EVM. The mapping of the switches are shown in the table below.
Table 26: Register 725, CCD Internal I/O Read/Write Register 1
Bit # Signal State Action
7 0 = GPIO_0.7
Write bit when DIR = 0
Read bit when DIR = 1
6 0 = GPIO_0.6
Write bit when DIR = 0
Read bit when DIR = 1
5 0 = GPIO_0.5
Write bit when DIR = 0
Read bit when DIR = 1
4 0 = GPIO_0.4
Write bit when DIR = 0
Read bit when DIR = 1
3 0 = GPIO_0.3
Write bit when DIR = 0
Read bit when DIR = 1
2 0 = GPIO_0.2
Write bit when DIR = 0
Read bit when DIR = 1
1 0 = GPIO_0.1
Write bit when DIR = 0
Read bit when DIR = 1
0 0 = GPIO_0.0
Write bit when DIR = 0
Read bit when DIR = 1
Table 27: Key Pad Layout
Key-A0 Key-A0 Key-A1 Key-A1
Key-B0 SW6 / KEY 2 SW7 / LEFT SW8 / EXIT SW9 / DOWN
Key-B0 SW10 / ENTER SW11 / UP SW12 KEY 1 SW13 / RIGHT
Key-B1 SW14 / MENU SW15 / REC SW16 / REW SW17 / SKIP-
Key-B1 SW18 / STOP SW19 / FF SW20 / SKIP+ SW2 / PLAY/
PAUSE