Spectrum Digital TMS320DM368, Technical Reference

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Spectrum Digital, Inc
2-20 DM368 EVM Technical Reference
2.1.1.2.26 Register 723, CCD Internal I/O Read/Write Register 2
Register 723 is a 8 bit, read/write register that controls CPLD GPIO input on read, and
out value on write. The default data is 0b00000000. The table below shows the
mapping of these bits.
2.1.1.2.27 Register 724, CCD Internal I/O Direction Register 3
Register 724 is a 8 bit, read/write register that controls CPLD GPIO to CCD Connector
pin input/output mapping. The default data is 0b11111111. The table below shows the
mapping of these bits.
Table 24: Register 723, CCD Internal I/O Read/Write Register 2
Bit # Signal State Action
7 0 = GPIO_0.7
Write bit when DIR = 0
Read bit when DIR = 1
6 0 = GPIO_0.6
Write bit when DIR = 0
Read bit when DIR = 1
5 0 = GPIO_0.5
Write bit when DIR = 0
Read bit when DIR = 1
4 0 = GPIO_0.4
Write bit when DIR = 0
Read bit when DIR = 1
3 0 = GPIO_0.3
Write bit when DIR = 0
Read bit when DIR = 1
2 0 = GPIO_0.2
Write bit when DIR = 0
Read bit when DIR = 1
1 0 = GPIO_0.1
Write bit when DIR = 0
Read bit when DIR = 1
0 0 = GPIO_0.0
Write bit when DIR = 0
Read bit when DIR = 1
Table 25: Register 724, CCD Internal I/O Direction Register 3
Bit # Signal State Action
7 0 = GPIO_2.7DIR 0 = Outputs, 1 = Inputs
6 0 = GPIO_2.6DIR 0 = Outputs, 1 = Inputs
5 0 = GPIO_2.5DIR 0 = Outputs, 1 = Inputs
4 0 = GPIO_2.4DIR 0 = Outputs, 1 = Inputs
3 0 = GPIO_2.3DIR 0 = Outputs, 1 = Inputs
2 0 = GPIO_2.2DIR 0 = Outputs, 1 = Inputs
1 0 = GPIO_2.1DIR 0 = Outputs, 1 = Inputs
0 0 = GPIO_2.0DIR 0 = Outputs, 1 = Inputs