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— 115 —
Pin No.
44
45
46
47
48 to 51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
I/O
O
O
O
O
I/O
I
O
I(A)
—
I(A)
I(A)
—
O(3)
I(A)
O(A)
I(A)
I(A)
I(A)
I(A)
I(A)
I(A)
I(A)
O(A)
—
I(A)
I(A)
—
I(A)
I(A)
I(A)
I(A)
I
O
O
O
O
O
I
O
Description
Column address strobe signal output to the D-RAM (IC124)
Address output to the D-RAM (IC124)
Row address strobe signal output to the D-RAM (IC124)
Write enable signal output to the D-RAM (IC124)
Bi-directional data bus for the D-RAM (IC124)
Oscillation input from the external VCO for DIGITAL IN PLL. Not used in this unit (fixed at “L”)
Playback EFM full-swing output
Playback EFM asymmetry comparate voltage input
Power supply terminal (+3.3 V) (analog system)
Playback EFM asymmetry circuit constant current input
Playback EFM RF signal input from the CXA2523R (IC101)
Ground terminal (analog system)
Phase comparison output to master clock of the master PLL of record/playback EFM system
Filter input to master clock of the master PLL of record/playback EFM system
Filter output to master clock of the master PLL of record/playback EFM system
Control voltage input to internal VCO of the master PLL of the recording/playback EFM
Light amount signal (RF/ABCD) peak-hold input from the CXA2523AR (IC101)
Light amount signal (RF/ABCD) bottom-hold input from the CXA2523AR (IC101)
Light amount signal input from the CXA2523AR (IC101)
Focus error signal input from the CXA2523AR (IC101)
Auxiliary signal (I3 signal/temperature signal) input from the CXA2523AR (IC101)
Center point voltage (+1.65 V) input from the CXA2523AR (IC101)
Monitor output of the A/D converter input signal. Not used in this set
Power supply terminal (+3.3 V) (analog system)
A/D converter operation range’s upper limit voltage input (fixed at “H” in this set)
A/D converter operation range’s lower limit voltage input (fixed at “L” in this set)
Ground terminal (analog system)
Sled error signal input from the CXA2523AR (IC101)
Tracking error signal input from the CXA2523AR (IC101)
Connected to the +3.3 V power supply
Not used in this set (fixed at “H”)
ADIP duplex FM signal (22.05 kHz Å} 1 kHz) input from the CXA2523AR (IC101)
Filter f0 control signal output to the CXA2523AR (IC101)
Serial latch signal output to the CXA2523AR (IC101)
Serial clock signal output to the CXA2523AR (IC101)
Write data output to the CXA2523AR (IC101)
Signal output that controls the reference voltage generator circuit of the laser automatic power control and is
output to the CXA2523AR (IC101)
Not used in this set
Tracking servo drive PWM signal (–) output to the BH6511FS (IC152)
Pin Name
XCAS
A09
XRAS
XWE
D1 to D3
MVCI
ASYO
ASYI
AVDD
BIAS
RFI
AVSS
PCO
FILI
FILO
CLTV
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
AVDD
ADRT
ADRB
AVSS
SE
TE
DCHG
TEST4
ADFG
F0CNT
XLRF
CKRF
DTRF
APCREF
TEST0
TRDR
* The numeral 3 in parenthesis (3) in the I/O column means tri-state output. The letter (A) in the I/O column means the monitor output
during analog output mode.
Summary of Contents for HCD-MD555
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Page 74: ...HCD MD555 95 96 7 20 SCHEMATIC DIAGRAM PANEL SECTION Refer to page 110 for IC Block Diagrams ...
Page 122: ... 148 MEMO HCD MD555 ...