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— 114 —
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19, 20
21
22
23
24
25
26
27
28
29
30
31 to 34
35
36 to 40
41
42
43
I/O
O
O
O
O
I
I
I
O(3)
O(3)
I
O
O
I
O
I
I
O
I
I
O
I
I
O
O
O
O
—
O
O
O
O
—
O
Description
Focus OK signal output to the MD mechanism controller (IC316). “H” is output when focus is on (“L”: NG)
Track jump detection signal output to the MD mechanism controller (IC316)
Busy signal output to the MD mechanism controller (IC316)
Monitor signal output to the MD mechanism controller (IC316)
Write data input from the MD mechanism controller (IC316)
Serial clock input from the MD mechanism controller (IC316)
Serial latch signal input from the MD mechanism controller (IC316)
Read data output to the MD mechanism controller (IC316)
Internal status (SENSE) output to the MD mechanism controller (IC316)
Reset signal input from the MD mechanism controller (IC316). “L”: reset
Subcode Q sync (SCOR) output to the MD mechanism controller (IC316). “L” is output every 13.3 mseconds.
“H” is output in most cases
Subcode Q sync (SCOR) output of the DIGITAL-IN U-bit CD format to the MD mechanism controller (IC316).
“L” is output every 13.3 mseconds. “H” is output in most cases
Laser power select signal input from the MD mechanism controller (IC316). “H”: record mode,
“L”: playback mode
Interrupt status output to the MD mechanism controller (IC316)
Record data output enable signal input from the MD mechanism controller (IC316).
Write data transfer timing is input. (Also serves as the magnetic head on/off output)
System clock (512Fs = 22.5792 MHz) input
System clock (512Fs = 22.5792 MHz) input (open in this set)
Input signal for setting the system clock frequency. “L”: 45.158 MHz, “H”: 22.5792 MHz.
Fixed at “H” in this set
Digital audio input signal for recording. (Either digital signal or optical input from CD is selected in this set.)
(DIN1 is not used in this set)
Digital audio signal output during playback mode (for DIGITAL OUTPUT). Not used in this set (open)
Not used in this set (open)
Record data input from A/D, D/A converter (IC201)
Playback data output to A/D, D/A converter (IC201)
L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC201)
Bit clock signal (2.8224 MHz) output to serial input/output data to the A/D, D/A converter (IC201)
Clock signal (11.2896 MHz) output to the A/D, D/A converter (IC201)
Power supply terminal (+3.3 V) (digital system)
Address output to the D-RAM (IC124)
Address output to external D-RAM. Not used in this set (open)
Address output to D-RAM (IC124)
Address output to external D-RAM. Not used in this set (open)
Ground terminal (digital system)
Output enable signal output to D-RAM (IC124)
Pin Name
MNT0
(FOK)
MNT1
(SHCK)
MNT2
(XBUSY)
MNT3
(SLOC)
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
DINO,
DINI
DOUT
DADTI
LRCKI
XBCKI
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03 to A00
A10
A04 to A08
A11
DVSS
XOE
•
IC121 DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER) (CXD2654AR) (BD (MD) BOARD)
* The numeral 3 in parenthesis (3) in the I/O column means tri-state output. The letter (A) in the I/O column means the monitor output
during analog output mode.
Summary of Contents for HCD-MD555
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Page 74: ...HCD MD555 95 96 7 20 SCHEMATIC DIAGRAM PANEL SECTION Refer to page 110 for IC Block Diagrams ...
Page 122: ... 148 MEMO HCD MD555 ...