Sony HCD-MD555, Service Manual

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Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
O
I
I
—
I
I
I
O
I
—
I
—
—
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
O
—
O
O
O
O
O
O
—
I
I
I
I
I
I
Description
SubQ 80-bit, PCM peak and level data output CD TEXT data output
Clock input to read out SQSO
System reset. “L”: reset
Connected to ground terminal
Serial data input from CPU
Latch input from CPU. Serial data is latch at rise-up
Serial data transfer clock input from CPU
SENS output. Output to CPU
Clock input to read the SENS serial data
Power supply
Input/output for anti-shock (connected to ground terminal)
Not used (fixed at “L”)
Not used (fixed at “L”)
Laser diode switch output
WFCK output
XUGF output. MNT0, RFCK output when selected command
XPCK output. MNT1 output when selected command
GFS output MNT2, XROF output when selected command
C2PO output MNT3, GTOP output when selected command
“H” output when either subcode sync S0 or S1 is detected. (Not used)
Number of tracks counting signal input/output
Mirror signal input/output
Defect signal input/output
Focus OK signal input/output
GFS is sampled by 460 Hz. “H” output when GFS is “H”. “L” output when GFS is “L” eight times
continuously. Input mode when LKIN = “1”
Spindle motor servo control output
Disc innermost circumference detection signal input
Sled drive output
Tracking drive output
Focus drive output
Ground terminal
TEST terminals. Normally grounded terminal
Connected to ground terminal
Center point voltage input
Focus error signal input
Sled error signal output
Pin Name
SQSO
SQCK
XRST
SYSM
DATA
XLAT
CLOK
SENS
SCLK
VDD
ATSK
SPOA
SPOB
XLON
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
COUT
MIRR
DFCT
FOK
LOCK
MDP
SSTP
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
VSS
TEST
TES1
XTSL
VC
FE
SE
7-25. IC Pin Function Description
•
IC101 Digital Signal Processor (CXD2587Q) (BD (CD) Board)