Sony DMBK-S101, Service Manual

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5-2
SIU-100/100T
(1) Entire unit control by CPU (IC101)
The CPU block controls the entire SIU-100/100T unit.
The CPU block is composed of the CPU, FLASH Memory
(IC200, 201), SDRAM (IC300), SRAM (IC202), Address
Decoder (IC503), and bus buffer IC.
.
The CPU firmware is written in the Flash Memory
(IC200, 201). The Flash Memory stores the unit serial
number set at the factory, the MAC address of the
Ethernet, and also the scene information saved by a user.
.
The SDRAM (IC300) is the main memory for the CPU.
.
The SRAM (IC202) is the memory for the CPU as the
SDRAM. It is backed up with the battery (BT201) after
the power-off. The SRAM stores the information
necessary to keep even after the power-off.
.
The PLD (IC503) mainly functions as an address
decoder for the CPU.
.
The CPU bus is connected to the CP-383 board and the
eight option slots through the bus buffer, CN1000, and
CN1001 to communicate.
.
Through the buffer, the CPU controls the connectors
(Ethernet, MIDI IN, and REMOTE connectors) for
controlling the SIU100 from outside.
(2) FPGA Block
The two FPGAs IC700 and IC703 perform the routing
process of the audio signal between the option slots.
IC700 and IC703 are connected with the eight option slots
through CN1000 and CN1001 to input/output the audio
signal.
After the unit starts, the CPU writes the firmware into
IC700 and IC703 (Configuration). After the configuration,
the LED (D701) lights and the FPGA starts the operation.
The routing is controled by writing necessary data in
IC700 and 703 from the CPU.
(3) SYNC Block
The SYNC block generates the audio system clock of the
SIU-100/100T, and supplies it to the FPGA block, all
option slots, and CP-383 board.
The SYNC block composed of the video PLL block and
the main PLL block.
The video PLL block is used for the internal synchroniza-
tion and the external video (EXT-VIDEO) synchroniza-
tion.
The main PLL block is always in operation to generate the
audio system clock necessary for the internal operation.
Operation during each synchronization
INTERNAL synchronization:
The video PLL block does not perform the PLL operation.
One of X1300, 1301, and 1032 self-generates the clock
with 100 times frequency of word clock (sampling fre-
quency). This clock is divided by 100 to generate the word
clock. From the generated word clock, the main PLL block
of the back stage generates the audio system clock (such as
256fx, BCK (64fs), or LRCK (1fs)).
VIDEO synchronization:
From the video signal input from external connector, the
sync separator block (IC1101) is output the vertical sync
signal of the video to supply to the video PLL block. The
video PLL block generates the word clock synchronized
with the vertical sync signal of the video. From the gener-
ated word clock, the main PLL block of the back stage
generates the necessary clock (such as 256fx, BCK (64fs),
or LRCK (1fs)).
EXT-WORD synchronization:
From the word clock input from the external connector, the
main PLL generates the necessary audio clock.
EXT-DI synchronization: From the word clock sent from
the option slot, the main PLL generates the necessary
audio clock. The CPU determines the slot to send the clock
by directing its board.
IC1400 operation:
The PLD (IC1400) performs the following operations to
control the entire SYNC block:
.
Input/Output port of CPU:
When the CPU bus-accesses IC1400, IC1400 outputs the
signal to switch the SYNC block oprations, or sends to
the CPU the signal including the hardware operation
status.
.
PLL dividers:
Generates the timing signals as a part of the video and
main PLLs.
.
Lock/Unlock determination for main PLL:
Determines the Lock/Unlock for mail PLL to be read by
the CPU.
.
Clock generations:
From the master clock (512fs) output from the main
PLL, generates the clock, such as 256fs, BCK (64fs),
LRCK (1fs), XWS, or WSA by making the counters
operate.