Sony DMBK-S101, Service Manual

Page: 82 / 162

4-4
SIU-100/100T
1 2 3 4 5
VOLTAGE DETECTION SYSTEM RESET
—SIDE VIEW—
V
CC
NC
GND
CD
OUT
+
+
_
5 u A
OUT
5
GND
3
1.25 V
V
CC
1
CD
4
M51954BL (MITSUBISHI)
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
6 5 4 3 2 1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
PROGRAMMABLE LOGIC DEVICE
—TOP VIEW—
1
2
3
4
5
6
7
8
9
10
11
I
I
—
I/O
I/O
I/O
I/O
I/O
I/O
—
—
INPUT/
GCLR
INPUT/
OE2
V
CC
I/O
I/O
I/O
I/O (TDI)
I/O
I/O
GND
V
CC
12
13
14
15
16
17
18
19
20
21
22
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
—
I/O
I/O (TMS)
I/O
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
GND
23
24
25
26
27
28
29
30
31
32
33
—
I/O
I/O
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O (TCK)
I/O
34
35
36
37
38
39
40
41
42
43
44
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
—
I
I
I/O
V
CC
I/O
I/O
I/O (TDO)
I/O
I/O
I/O
GND
INPUT/GCLK1
INPUT/
OE1
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
*
ABOVE DIAGRAM SHOWS CONDITIONS BEFORE PROGRAMMING
GCLK1
GCLR
OE1
OE2
43
1
44
2
4 - 9,
12 - 14,
16 - 21
PIA
16 16 16 16 16
16 16
16
24 - 29,
31 - 34,
36 - 41
I/O
CONTROL
BLOCK
MACROCELL
(1 - 16)
I/O
CONTROL
BLOCK
MACROCELL
(17 - 32)
I/O
I/O
EPM7032SLC44-10(05) (ALTERA)
IC
DUAL 24-BIT A/D CONVERTER
—TOP VIEW—
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIN
NO.
1
2
3
4
5
6
7
I/O
O
—
O
I
I
I
—
SIGNAL
VREFL
GNDL
VCOML
AINL
+
AINL
_
ZCAL
D.V
CC
PIN
NO.
8
9
10
11
12
13
14
I/O
—
O
O
I
I
I/O
I/O
SIGNAL
D.GND
CAL
RST
SMODE2
SMODE1
LRCK
SCLK
PIN
NO.
15
16
17
18
*
19
20
21
I/O
O
I/O
I
I
*
I
I
—
SIGNAL
SDATA
FSYNC
MCLK
CMODE/DFS
*
HPFE
TEST
BGND
* : NOTE
CMODE
DFS
: AK5392
: AK5393 , AK5383
PIN
NO.
22
23
24
25
26
27
28
I/O
—
—
I
I
O
—
O
SIGNAL
A.GND
A.V
CC
AINR
_
AINR
+
VCOMR
GNDR
VREFR
INPUTS
AINL + , AINL _ ,
AINR + , AINR _
CMODE
DFS
HPFE
MCLK
RST
SMODE1, SMODE2
TEST
ZCAL
OUTPUTS
CAL
SDATA
VCOML, VCOMR
VREFL, VREFR
INPUTS/OUTPUTS
FSYNC
LRCK
SCLK
OTHERS
A.GND
A.V
CC
BGND
D.GND
D.V
CC
GNDL, GNDR
: L/R CH ANALOG
: MASTER CLOCK SELECT (L: 256fs, H: 384fs)
: DOUBLE FAST SAMPLING MODE SELECT
: HPF ENABLE
: MASTER CLOCK
: RESET
: SERIAL INTERFACE MODE SELECT
: TEST
: ZERO CALIBRATION
: CALIBRATION STATUS
: SERIAL DATA
: L/R CH COMMON VOLTAGE
: L/R CH REFERENCE VOLTAGE
: FRAME SYNC CLOCK
: L/R CH SELECT CLOCK
: SERIAL DATA CLOCK
: ANALOG GROUND
: ANALOG POWER SUPPLY
: BOARD GROUND
: DIGITAL POWER SUPPLY
: DIGITAL GROUND
: L/R CH REFERENCE GROUND
AK5383VF-E2 (AKM)
SDATA
15
HPFE
MCLK
CMODE/DFS
*
19
17
18
CAL
9
SCLK
LRCK
FSYNC
14
13
16
SMODE1, SMODE2
VCOML
AINL
+
, AINL
_
ZCAL
AINR
+
, AINR
_
VCOMR
RST
3
12, 11
4, 5
∆
∑
MODULATOR
25, 24
6
∆
∑
MODULATOR
DECIMATION
FILTER
SERIAL OUTPUT INTERFACE
DECIMATION
FILTER
10
26
VREFL, VREFR
GNDR, GNDR
1, 28
2, 27
VOLTAGE
REFERENCE
CONTROLLER
HPF
HPF
CALIBRATION
SRAM
* : NOTE
CMODE
DFS : AK5392
: AK5393, AK5383