Sony DMBK-S101, Service Manual

Page: 83 / 162

4-5
SIU-100/100T
1
2
3
4
5
10
9
8
7
6
LDO
OUT
FREQ
IN
A.GND
REF
OUT
FB
IN
SYNC/
SHDN
IN
V
CC
EXT
OUT
P.GND
CS +
IN
INPUTS
CS +
FB
FREQ
SHDN
SYNC
OUTPUTS
EXT
LDO
REF
OTHER
P.GND
: POSITIVE CURRENT DETECT
: FEEDBACK
: OSCILLATION FREQUENCY SET
: SHUTDOWN
: SYNC
: EXTERNAL MOS-FET GATE DRIVER
: INTERNAL REGULATOR (5 V)
: REFERENCE VOLTAGE (1.25 V)
: GROUND FOR EXT GATE DRIVER OR NEGATIVE
CURRENT DETECT
PWM STEP-UP CONTROLLER
—TOP VIEW—
+
_
+
+ A
x 6
x
1
x
1
_
_ A
+ C
_ C
SLOPE
COMPENSATION
MAIN PWM
COMPARATOR
+ S
_ S
MUX
0
1
Q
OSCILLATOR
BIAS
R
S
ANTISAT
SYNC/
SHDN
FREQ
10
2
EXT
P.GND
REF
8
7
4
LDO
1
FB
1.25 V
100 mV
I
MIN
I
MAX
UVLO
15 mV
1.25 V
5
CS +
6
V
CC
9
MAX668EUB-TG069 (MAXIM)
STEP UP/DOWN/INVERTING SWITCHING REGULATOR
1 : GATE
2 : MIRROR
3 : DRAIN
4 : KELV
IN
5 : SOURCE
OSC.
THERMAL
SHUTDOWN
5.05 V
REFERENCE
+
_
+
+
C
T
PWM LATCH
UNDER VOLTAGE
LOCK OUT
ERROR
AMP.
CURRENT
SENSE
PWM
Q
R
S
+
_
+
_
+
100 u A
_
+
+
SOURCE
5
GATE
1
MIRROR
2
KELV
IN
4
1
2
3
4
5
DRAIN
3
MC33166TV (ON SEMICONDUCTOR)
IC
1 5
10 15 20 25 30 35 36
108 105 100 95 90 85 80 75 73
109
110
115
120
125
130
135
140
144
72
70
65
60
55
50
45
40
37
FIELD PROGRAMMABLE GATE ARRAY
—TOP VIEW—
—
I
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
—
I
—
—
I
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
I/O
I/O
I
—
O
—
—
V
CC
TCK
IO
IO
IO/V
REF
IO
IO
GND
V
CCINT
IO
IO
IO/V
REF
IO
V
CCINT
I/GCK3
V
CC
GND
I/GCK2
IO
IO
IO/V
REF
IO
IO
V
CCINT
GND
IO
IO
IO/V
REF
IO
IO/
WRITE
IO/
CS
TDI
GND
TDO
V
CC
V
CC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I/O
—
I/O
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
—
—
I/O
CCLK
IO/DOUT/BUSY
IO/DIN/D0
IO
IO/V
REF
IO
IO
IO/D1
GND
IO/D2
IO
IO/V
REF
IO/D3
IO
IO/IRDY1
GND
V
CC
IO/TRDY1
V
CCINT
IO
IO/D4
IO/V
REF
IO
IO/D5
GND
IO/D6
IO
IO
IO/V
REF
IO
IO/D7
IO/
INIT
PROGRAM
V
CC
V
CC
DONE
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
I/O
I
—
—
I
—
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
I/O
—
—
I
—
—
GND
IO
IO
IO
IO/V
REF
IO
IO
IO
GND
V
CCINT
IO
IO
IO/V
REF
IO
IO
I/GCK0
GND
V
CC
I/GCK1
V
CCINT
IO
IO/V
REF
IO
IO
V
CCINT
GND
IO
IO
IO
IO/V
REF
IO
NC
NC
M2
V
CC
V
CC
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
I
—
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
—
I/O
—
—
I/O
I/O
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
I
—
—
M0
GND
M1
IO
IO
IO
IO/V
REF
IO
IO
IO
GND
IO
IO
IO/V
REF
IO
IO
V
CCINT
IO/TRDY2
V
CC
GND
IO/IRDY2
IO
IO
IO/V
REF
IO
IO
GND
IO
IO
IO
IO/V
REF
IO
IO
TMS
GND
V
CC
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
INPUTS
CS
D0 - D7
DIN
GCK0 - GCK3
M0 - M2
PROGRAM
TCK
TDI
TMS
V
REF
WRITE
OUTPUTS
BUSY/DOUT
DONE
TDO
INPUTS/OUTPUTS
CCLK
INIT
OTHER
NC
: CHIP SELECT SIGNAL
: DATA
: SERIAL CONFIGURATION DATA
: GLOBAL CLOCK
: MODE
: PROGRAM
: TEST CLOCK
: TEST DATA
: TEST MODE SELECT
: REFERENCE VOLTAGE
: WRITE ENABLE SIGNAL
: BUSY/SERIAL CONFIGURATION DATA
: INPUT FOR DELAYING THE GLOBAL LOGIC INITIALIZATION & OUTPUT ENABLE
/OUTPUT FOR INDICATING THE COMPLETION OF THE CONFIGURATION
: TEST DATA
: CONFIGURATION CLOCK
: INTERNAL CONFIGURATION MEMORY CLEAR
: NO CONNECTION
XC2S50-5TQ144C1 (XILINX)