Sony BVP-900 Series, Maintenance Manual

Page: 154 / 520

2-28
BVP-900
BVP-900P
IC
OPERATIONAL AMPLIFIER
(J FET INPUT)
V
EE
(-18V)
V
CC
(+18V)
1
2
3
4
5
6
7 8
9
10
11
12
13
14
+ _ + _
+ _ + _
—TOP VIEW—
CLR
0
1
0
1
1
1
PR
1
0
0
1
1
1
CK
X
X
X
D
X
X
X
0
1
X
Qn + 1
0
1
1
0
1
Qn
Qn + 1
1
0
1
1
0
Qn
INPUTS OUTPUTS
0
1
X
2
1
5
6
3
7
CLR
D
Q
Q
PR
(SCALE 3/1)
1
2
3
6
7
8 V
DD
GND 4 5
TYPE
7W74F
7W74FU
7WH74FU
V
DD
+2 to
+
6V
+ 2 to + 5.5V
FUNCTION
CLEAR
PRESET
–
–
–
NO CHANGE
; LOW LEVEL
; HIGH LEVEL
; DON'T CARE
C-MOS D-TYPE FLIP-FLOPS WITH PRESET AND CLEAR
—TOP VIEW—
1
2
3
4
8
7
6
5 GND
V
DD
( + 2 to + 6 V)
1
2
A
B
7 Y
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
1
0 ; LOW LEVEL
1 ; HIGH LEVEL
C-MOS DUAL 2-INPUT OR GATE
A
B
Y
Y = A + B = A • B
5
6
3
—TOP VIEW—
C-MOS 2-INPUT AND GATE
(SCALE 3/1)
—TOP VIEW—
1
2
3
8 V
DD( + 2 to + 6V)
6
7
GND 4 5
A
B
A
B
Y =
1
2
7
Y
A
0
0
1
1
Y
0
0
0
1
B
0
1
0
1
0 ; LOW LEVEL
1 ; HIGH LEVEL
Y = A • B = A
+
B
3
5
6
C-MOS DUAL 2-INPUT NOR GATE
( + 2 to + 6V)
V
DD
1
2
3
4
1A
1B
2Y
1Y
2B
2A 5
6
7
8
GND
A
B
A
B
Y =
Y
A
0
0
1
1
B
0
1
0
1
Y
1
0
0
0
0 ; LOW LEVEL
1 ; HIGH LEVEL
Y = A + B = A • B
—TOP VIEW—
TC7W02F (TOSHIBA)FLAT PACKAGE
TC7W02FU(TE12R)
TC7W04FU(TE12R) (TOSHIBA)FLAT PACKAGE
TC7W08FU (TOSHIBA)CHIP PACKAGE
TC7W08FU(TE12R)
TC7W139FU(TE12R) (TOSHIBA)CHIP PACKAGE
TC7W32FU (TOSHIBA)CHIP PACKAGE
TC7W32FU(TE12R)
TC7W74FU (TOSHIBA)CHIP PACKAGE
TC7W74FU(TE12R)
TC7WH74FU(TR12R) (TOSHIBA)CHIP PACKAGE
TL064CPW (TI)FLAT PACKAGE
TL064CPW-E05
UPA101G (NEC)FLAT PACKAGE
UPA101G-E2
1
2
3
8 V
DD( + 2 to + 6V)
6
7
GND 4
5
A A Y =
1 7
Y
A
0
1
Y
1
0
0 ; LOW LEVEL
1 ; HIGH LEVEL
Y = A
3 5
6 2
C-MOS HEX INVERTERS
—TOP VIEW—
C-MOS 2 to 4 LINE DECODER WITH ENABLE
—TOP VIEW—
F TYPE
FU TYPE
V
DD
( + 2 to + 6V)
5
6
7
8
GND 4
3
2
1
1
2
A
B
Y0
Y1
Y2
Y3
7
6
5
3
B
0
0
1
1
A
0
1
0
1
Y0
0
1
1
1
Y1
1
0
1
1
Y2
1
1
0
1
Y3
1
1
1
0
Y0
Y1
Y2
Y3
INPUTS
SELECT
SELECTED
OUTPUT
OUTPUTS
0 ; LOW LEVL
1 ; HIGH LEVEL
(SCALE 5/1)
5
6
7
8
GND 4
3
2
1
(SCALE 5/1)
V
DD
( + 2 to + 6V)
TRANSISTOR ARRAY
1 2 3 4
8 7 6 5
—TOP VIEW—