Sony BVP-900 Series, Maintenance Manual, Page: 148 / 520

2-22
BVP-900
BVP-900P
IC
MN8232A (MATSUSHITA)
PICTURE IN PICTURE/PICTURE OUT PICTURE CONTROLLER
—TOP VIEW—
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
V
DD ( + 5 V)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
V
DD ( + 5 V)
V
DD ( + 5 V)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND GND V
DD
(
+
5 V
)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND
V
DD
(
+
5 V
)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
—
—
—
I
I
I
I
—
—
I
—
I
I
O
I
I
GND
GND
VRB
TEST0
Y
RY
BY
V
DD
VRT
TEST1
V
DD
IREF
VREF
Y
COMP
VIB
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
O
O
—
I
I
O
I
I
I
I
O
I
—
I
—
O
RY
BY
GND
RST
SCL
SDA
VPD
VCD
CKCNT
CVC
CPC
HC
GND
IREFVC
V
DD
CLAMP
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
O
I
O
I
—
—
O
O
O
O
O
O
O
O
O
O
YS
HP
PPC
PVC
V
DD
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
CAS
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
O
O
O
O
I
I
I
—
—
I
I
I
O
O
O
O
RAS
WE
DT
SC
LEV1
LEV0
DI3
V
DD
GND
DI2
DI1
DI0
DO3
DO2
DO1
DO0
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
GND
MSM82C51A-2GS-K (OKI)FLAT PACKAGE
CS
1
0
0
0
0
0
0
1
x
HI-Z
: LOW LEVEL
: HIGH LEVEL
: DON’T CARE
: HIGH IMPEDANCE
C-MOS PROGRAMMABLE COMMUNICATION INTERFACE
—TOP VIEW—
D2
I/O
D3
I/O
RXD
IN
D4
I/O
D5
I/O
D6
I/O
D7
I/O
TXC
IN
WR
IN
CS
IN
C/
D
IN
RD
IN
RXRDY
OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD ( + 5 V)
NC
NC
D1
I/O
D0
I/O
RXC
IN
DTR
OUT
RTS
OUT
DSR
IN
RESET
IN
CK
IN
TXD
OUT
TXEMPTY
OUT
CTS
IN
SYNDET/BD
I/O
TXRDY
OUT
NC
GND
NC
23
14
15
11
12
24
25
27
19
26
CK
C/
D
RD
WR
CS
RESET
DSR
DTR
CTS
RTS
D0
D1
D2
D3
D4
D5
D6
D7
TXD
TXRDY
TXEMPTY
TXC
RXD
RXRDY
RXC
SYNDET/BD
31
32
1
2
6
7
8
9
22
17
21
10
3
16
28
18
C/
D
x
x
1
1
0
0
RD
x
1
0
1
0
1
WR
x
1
1
0
1
0
FUNCTION
DATA BUS 3-STATE
DATA BUS 3-STATE
STATUS TO CPU
CONTROL WORD FROM CPU
DATA TO CPU
DATA FROM CPU
OPERATION WITH CPU
TXD
22
DATA
BUS
BUFFER
D7 - D0
31, 32, 1, 2,
6, 7, 8, 9
READ/
WRITE
CONTROL
LOGIC
RESET
24
CK
23
C/
D
14
RD
15
WR
11
CS
12
MODEM
CONTROL
DSR
25
DTR
27
CTS
19
RTS
26
TRANSMIT
BUFFER
(P-S)
TXRDY
17
TXEMPTY
21
TXC
10
RECEIVE
BUFFER
(S-P)
RXD
3
RXRDY
RECEIVE
CONTROL
RXC
28
SYNDET/BD
18
16
INTERNAL
DATA BUS
TRANSMIT
CONTROL
SC
DT
WE
RAS
CAS
A8
A7
A6
A5
A4
A3
A2
A1
A0
52
51
50
49
48
47
46
45
44
43
42
41
40
39
EXTERNAL MEMORY CONTROL/
ADDRESS GENERATOR
60 59 58 55
DI0 DI1 DI2 DI3
64 63 62 61
DO0 DO1 DO2 DO3
54 53
LEV0 LEV1
MULTIPLEXER
STORE
BUFFER
MEMORY
Y
5
RY
6
BY
7
AD
CONVERTER
7
VERTICAL
FILTER
READ
BUFFER
MEMORY
DEMULTIPLEXER
FRAME COLOR
LEVEL
VREF
13
IREF
12
ELECTRIC
CURRENT FRAME
COMPOSITE
DA
CONVERTER
Y
14
COMP
15
VIB
16
7
DA
CONVERTER
RY
17
6
DA
CONVERTER
BY
18
6
VRB
3
VRT
9
STORE
CONTROL
I
2
C
CONTROL
READ
CONTROL
SAMPLING
CLOCK
GENERATOR
34 36 35
HP
PVC PPC
DISPLAY
CLOCK
GENERATOR
28 26 27
HC
CVC CPC
25 30
CKCNT
IREFVC
32 33
CLAMP
YS
21 22 20
SCL
SDA
RST
+
_
INPUT
CK
CS
CTS
C/
D
DSR
RD
RESET
RXC
RXD
TXC
WR
OUTPUT
DTR
RTS
RXRDY
TXD
TXEMPTY
TXRDY
INPUT/OUTPUT
D0 - D7
SYNDET/BD
: CLOCK SIGNAL
: CHIP ENABLE
: CLEAR TO SEND DATA
: DATA, COMMAND WORD OR STATUS WORD
IS TO BE WRITTEN OR READ
: DATA SET READY
: READ DATA OR STATUS WORD
: RESET BY HIGH LEVEL
: RECEIVING CLOCK
: RECEIVING DATA
: TRANSMITTING CLOCK
: WRITE DATA OR CONTROL WORD
: DATA TERMINAL READY
: REQUEST TO SEND DATA
: RECEIVING READY
: TRANSMITTING DATA
: TRANSMITTING CHARACTER EMPTY
: TRANSMITTING READY
: DATA
: SYNC DETECT/BREAK DETECT