SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 38
Version 0.1
3
3
3
RESET
3.1 OVERVIEW
The system would be reset in three conditions as following.
z
Power on reset
z
Watchdog
reset
z
Brown out reset
z
External reset (only supports external reset pin enable situation)
When any reset condition occurs, all system registers keep initial status, program stops and program counter is cleared.
After reset status released, the system boots up and program starts to execute from ORG 0. The NT0, NPD flags
indicate system reset status. The system can depend on NT0, NPD status and go to different paths by program.
086H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PFLAG
NT0 NPD
LVD36
LVD24 -
C DC Z
Read/Write
R/W R/W R
R
- R/W R/W R/W
After
reset
- - 0 0 - 0 0 0
Bit [7:6]
NT0, NPD:
Reset status flag.
NT0
NPD
Condition
Description
0
0
Watchdog reset
Watchdog timer overflow.
0 1
Reserved
-
1
0
Power on reset and LVD reset. Power voltage is lower than LVD detecting level.
1
1
External reset
External reset pin detect low level status.
Finishing any reset sequence needs some time. The system provides complete procedures to make the power on reset
successful. For different oscillator types, the reset time is different. That causes the VDD rise rate and start-up time of
different oscillator is not fixed. RC type oscillator’s start-up time is very short, but the crystal type is longer. Under client
terminal application, users have to take care the power on reset time for the master terminal requirement. The reset
timing diagram is as following.
VDD
VSS
VDD
VSS
Watchdog Normal Run
Watchdog Stop
System Normal Run
System Stop
LVD Detect Level
External Reset
Low Detect
External Reset
High Detect
Watchdog
Overflow
Watchdog
Reset Delay
Time
External
Reset Delay
Time
Power On
Delay Time
Power
External Reset
Watchdog Reset
System Status
