SN8P2711A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 67
Version 0.1
6.7 INT1 (P0.1) INTERRUPT OPERATION
When the INT1 trigger occurs, the P01IRQ will be set to “1” no matter the P01IEN is enable or disable. If the P01IEN =
1 and the trigger event P01IRQ is also set to be “1”. As the result, the system will execute the interrupt vector (ORG
8). If the P01IEN = 0 and the trigger event P01IRQ is still set to be “1”. Moreover, the system won’t execute interrupt
vector even when the P01IRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt
situation.
If the interrupt trigger direction is identical with wake-up trigger direction, the INT1 interrupt request flag (INT1IRQ) is
latched while system wake-up from power down mode or green mode by P0.1 wake-up trigger. System inserts to
interrupt vector (ORG 8) after wake-up immediately.
Note: INT1 interrupt request can be latched by P0.1 wake-up trigger.
Note: The interrupt trigger direction of P0.1 is falling edge.
¾
Example: INT1 interrupt request setup.
B0BSET
FP01IEN
;
Enable
INT1 interrupt service
B0BCLR
FP01IRQ
; Clear INT1 interrupt request flag
B0BSET
FGIE
; Enable GIE
¾
Example: INT1 interrupt service routine.
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
FP01IRQ
; Check P01IRQ
JMP
EXIT_INT
; P01IRQ = 0, exit interrupt vector
B0BCLR
FP01IRQ
; Reset P01IRQ
…
; INT1 interrupt service routine
…
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
