SONIX SN8P2711A User Manual Download

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SN8P2711A

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 79

Version 0.1

Example: Set P4.0 to be general purpose output. EVHENB and P4CON.0 bits must be set as “0”.

; Check EVHENB status.

B0BTS0

FEVHENB

; Check EVHENB = 0.

B0BCLR

FEVHENB

; EVHENB = 1, clear it to disable external ADC high
reference input.

; EVHENB = 0, execute next routine.

; Check GCHS and CHS[2:0] status.

B0BCLR

FGCHS

;If CHS[2:0] point to P4.0 (CHS[2:0] = 000B), set GCHS=0

;If CHS[2:0] don’t point to P4.0 (CHS[2:0]

≠

000B), don’t

care GCHS status.

; Clear P4CON.

B0BCLR

P4CON.0

; Enable P4.0 digital function.

; Set P4.0 output buffer to avoid glitch.

B0BSET

P4.0

; Set P4.0 buffer as “1”.

; or

B0BCLR

P4.0

; Set P4.0 buffer as “0”.

; Enable P4.0 output mode.

B0BSET

P4M.0

; Set P4.0 as input mode.

Summary of Contents for SN8P2711A

Page 1: ...s as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX product...

Page 2: ...SN8P2711A 8 Bit Micro Controller SONiX TECHNOLOGY CO LTD Page 2 Version 0 1 AMENDENT HISTORY Version Date Description VER 0 1 Jun 2007 First issue...

Page 3: ...ON 18 2 1 1 4 JUMP TABLE DESCRIPTION 20 2 1 1 5 CHECKSUM CALCULATION 22 2 1 2 CODE OPTION TABLE 23 2 1 3 DATA MEMORY RAM 24 2 1 4 SYSTEM REGISTER 25 2 1 4 1 SYSTEM REGISTER TABLE 25 2 1 4 2 SYSTEM REG...

Page 4: ...et Circuit 46 3 6 5 External Reset IC 47 4 4 4 SYSTEM CLOCK 48 4 1 OVERVIEW 48 4 2 CLOCK BLOCK DIAGRAM 48 4 3 OSCM REGISTER 49 4 4 SYSTEM HIGH CLOCK 50 4 4 1 INTERNAL HIGH RC 50 4 4 2 EXTERNAL HIGH CL...

Page 5: ...2 2 TC0M MODE REGISTER 84 8 2 3 TC1X8 TC0X8 TC0GN FLAGS 85 8 2 4 TC0C COUNTING REGISTER 85 8 2 5 TC0R AUTO LOAD REGISTER 87 8 2 6 TC0 CLOCK FREQUENCY OUTPUT BUZZER 88 8 2 7 TC0 TIMER OPERATION SEQUEN...

Page 6: ...EV KIT CONNECT TO SN8ICE 2K 120 12 5 TRANSITION BOARD FOR OTP PROGRAMMING 121 12 5 1 SN8P2711 V3 TRANSITION BOARD 121 12 5 2 SN8P2711 MP028A TRANSITION BOARD FOR EZ MPEZ WRITER 122 12 5 3 SN8P2711 MP...

Page 7: ...bit Timer Counter I O pin configuration TC0 Auto reload timer Counter PWM0 Buzzer output Bi directional P0 P4 P5 TC1 Auto reload timer Counter PWM1 Buzzer output Input only P0 4 shared with reset pin...

Page 8: ...ten at 0xnnFE and 0xnnFF ROM address No limitation 32KHz oscillator mode Not support Support 32KHz mode Firmware comparison SN8P2711 SN8 file can program into SN8P2711A OTP directly by EZ MP writer SN...

Page 9: ...L EXTERNAL HIGH OSC ACC INTERNAL LOW RC INTERNAL HIGH RC TIMING GENERATOR RAM SYSTEM REGISTERS LVD Low Voltage Detector WATCHDOG TIMER PWM 1 BUZZER 1 TIMER COUNTER P0 P5 P4 12 BIT ADC PWM 0 BUZZER 0 A...

Page 10: ...2 XOUT 3 12 P4 3 AIN3 P0 4 RST VPP 4 11 P4 2 AIN2 P5 3 BZ1 PWM1 5 10 P4 1 AIN1 P5 4 BZ0 PWM0 6 9 P4 0 AIN0 VREFH P0 1 INT1 7 8 P0 0 INT0 SN8P2711AP SN8P2711AS SN8P2711AX SSOP 16 pins VDD 1 U 16 VSS P...

Page 11: ...nction XOUT Oscillator output pin while external crystal enable P0 0 INT0 I O Port 0 0 bi direction pin Schmitt trigger structure as input mode Built in pull up resisters Built in wakeup function INT0...

Page 12: ...1 5 PIN CIRCUIT DIAGRAMS Port 0 2 P0 3 structure Oscillator Code Option Int Osc Pull Up Pin Output Latch PnM PnUR Input Bus PnM Output Bus Port 0 4 structure Pin Ext Reset Code Option Int Bus Int Rst...

Page 13: ...NOLOGY CO LTD Page 13 Version 0 1 Port 4 0 structure Int VERFH Pin EVHENB GCHS Int ADC P4CON Pull Up Output Latch PnM PnUR Input Bus PnM Output Bus Port 4 structure GCHS Int ADC P4CON Pull Up Output L...

Page 14: ...2 1 MEMORY MAP 2 1 1 PROGRAM MEMORY ROM 1K words ROM ROM 0000H Reset vector User reset vector Jump to user start address 0001H 0007H General purpose area 0008H Interrupt vector User interrupt vector 0...

Page 15: ...ternal reset or watchdog timer overflow reset then the chip will restart the program from address 0000h and all system registers will be set as default values It is easy to know reset status from NT0...

Page 16: ...wing example shows the way to define the interrupt vector in the program memory Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP buffer is a unique buffer and only one level...

Page 17: ...am User program JMP START End of user program MY_IRQ The head of interrupt service routine PUSH Save ACC and PFLAG register to buffers POP Load ACC and PFLAG register from buffers RETI End of interrup...

Page 18: ...set lookup table1 s low address MOVC To lookup data R 00H ACC 35H Increment the index address for next address INCMS Z Z 1 JMP F Z is not overflow INCMS Y Z overflow FFH 00 Y Y 1 NOP MOVC To lookup da...

Page 19: ...ord 16 bits data DW 5105H DW 2012H The other example of look up table is to add Y or Z index register by accumulator Please be careful if carry happen Example Increase Y and Z register by B0ADD ADD in...

Page 20: ...ACC PCH adds one automatically If PCL borrow after PCL ACC PCH keeps value and not change Example Jump table ORG 0X0100 The jump table is from the head of the ROM boundary B0ADD PCL A PCL PCL ACC PCH...

Page 21: ...egin from next RAM boundary 0x0100 Example JMP_A operation Before compiling program ROM address B0MOV A BUF0 BUF0 is from 0 to 4 JMP_A 5 The number of the jump table listing is five 0X00FD JMP A0POINT...

Page 22: ...o end_addr2 CLR Y Set Y to 00H CLR Z Set Z to 00H MOVC B0BSET FC Clear C flag ADD DATA1 A Add A to Data1 MOV A R ADC DATA2 A Add R to Data2 JMP END_CHECK Check if the YZ address the end of code AAA IN...

Page 23: ...In Fosc 2 Noise Filter must be disabled Fhosc 4 Instruction cycle is 4 oscillator clocks Fhosc 8 Instruction cycle is 8 oscillator clocks Fcpu Fhosc 16 Instruction cycle is 16 oscillator clocks Reset...

Page 24: ...NiX TECHNOLOGY CO LTD Page 24 Version 0 1 2 1 3 DATA MEMORY RAM 64 X 8 bit RAM Address RAM location 000h 03Fh General purpose area 080h 080h 0FFh of Bank 0 store system registers 128 bytes System regi...

Page 25: ...ration register VREFH ADC high reference voltage register ADM ADC s mode register ADB ADC data buffer ADR ADC resolution selection register PnM Port n input output mode register PEDGE P0 0 edge direct...

Page 26: ...P02 P01 P00 R W P0 0D4H P44 P43 P42 P41 P40 R W P4 0D5H P54 P53 R W P5 0D8H TC1X8 TC0X8 TC0GN R W T0M 0DAH TC0ENB TC0rate2 TC0rate1 TC0rate0 TC0CKS ALOAD0 TC0OUT PWM0OUT R W TC0M 0DBH TC0C7 TC0C6 TC0...

Page 27: ...by B0MOV instruction during the instant addressing mode Example Read and write ACC value Read ACC data and store in BUF data memory MOV BUF A Write a immediate data into ACC MOV A 0FH Write ACC data...

Page 28: ...by external Reset Pin Bit 5 LVD36 LVD 3 6V operating flag and only support LVD code option is LVD_H 0 Inactive VDD 3 6V 1 Active VDD 3 6V Bit 4 LVD24 LVD 2 4V operating flag and only support LVD code...

Page 29: ...t 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 After reset 0 0 0 0 0 0 0 0 0 0 PCH PCL ONE ADDRESS SKIPPING There are nine instructions CMP...

Page 30: ...C0STEP Jump to C0STEP if ACC is not zero C0STEP NOP INCMS instruction INCMS BUF0 JMP C0STEP Jump to C0STEP if BUF0 is not zero C0STEP NOP If the destination decreased by 1 which results underflow of 0...

Page 31: ...hree instructions and don t care PCL overflow problem Note PCH only support PC up counting result and doesn t support PC down counting When PCL is carry after PCL ACC PCH adds one automatically If PCL...

Page 32: ...After reset 083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 Read Write R W R W R W R W R W R W R W R W After reset Example Uses Y Z register as...

Page 33: ...byte data of look up table MOVC instruction executed the high byte data of specified ROM address will be stored in R register and the low byte data will be stored in ACC 082H Bit 7 Bit 6 Bit 5 Bit 4...

Page 34: ...gister 2 2 2 DIRECTLY ADDRESSING MODE The directly addressing mode moves the content of RAM location in or out of ACC Example Move 0x12 RAM location data into ACC B0MOV A 12H To get a content of RAM l...

Page 35: ...service routine and CALL instruction are executed The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer The STKnH and STKnL are the stack buf...

Page 36: ...terrupt service routine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 0DFH Bit 7 Bit 6 Bit...

Page 37: ...Byte Description 0 1 1 1 Free Free 1 1 1 0 STK0H STK0L 2 1 0 1 STK1H STK1L 3 1 0 0 STK2H STK2L 4 0 1 1 STK3H STK3L 4 0 1 0 Stack Over error There are Stack Restore operations correspond to each push o...

Page 38: ...Description 0 0 Watchdog reset Watchdog timer overflow 0 1 Reserved 1 0 Power on reset and LVD reset Power voltage is lower than LVD detecting level 1 1 External reset External reset pin detect low le...

Page 39: ...by program Under error condition system is in unknown situation and watchdog can t be clear by program before watchdog timer overflow Watchdog timer overflow occurs and the system is reset After watc...

Page 40: ...t touch the below area and not effect the system operation But the V2 and V3 is under the below area and may induce the system error occurrence Let system under dead band includes some conditions DC...

Page 41: ...perating voltage rises when the system executing rate upper even higher than system reset voltage The dead band definition is the system minimum operating voltage above the system reset voltage 3 4 3...

Page 42: ...e LVD can t be the protection and need to other reset methods More detail LVD information is in the electrical characteristic section The LVD is three levels design 2 0V 2 4V 3 6V and controlled by LV...

Page 43: ...hdog is continuously counting until overflow occurrence The overflow signal of watchdog timer triggers the system to reset and the system return to normal mode after reset sequence This method also ca...

Page 44: ...tem keeps reset status and waits external reset pin released z System initialization All system registers is set as initial conditions and system is ready z Oscillator warm up Oscillator operation is...

Page 45: ...Diode RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Electrical Over str...

Page 46: ...value to conform the application In the circuit diagram condition the MCU s reset pin level varies with VDD voltage variation and the differential voltage is 0 7V If the VDD drops and the voltage low...

Page 47: ...VCC GND RST Reset IC VDD VSS RST Bypass Capacitor 0 1uF The external reset circuit also use external reset IC to enhance MCU reset performance This is a high cost and good effect solution By different...

Page 48: ...tem clock Fosc The system clock in slow mode is divided by 4 to be the instruction cycle Fcpu Normal Mode High Clock Fcpu Fhosc N N 1 16 Select N by Fcpu code option Slow Mode Low Clock Fcpu Flosc 4 S...

Page 49: ...e run stop Internal low speed RC oscillator is still running Bit 2 CLKMD System high Low clock mode control bit 0 Normal dual mode System clock is high clock 1 Slow mode System clock is internal low c...

Page 50: ...ck is external oscillator The typical frequency is 4MHz 4 4 1 INTERNAL HIGH RC The chip is built in RC type internal high clock 16MHz controlled by IHRC_16M coed option In IHRC_16M mode the system clo...

Page 51: ...ex 4MHz 32K option is for low speed ex 32768Hz MCU VCC GND C 20pF XIN XOUT VDD VSS C 20pF CRYSTAL Note Connect the Crystal Ceramic and C as near as possible to the XIN XOUT VSS pins of micro controlle...

Page 52: ...ernal clock signal input to be system clock is by RC option of High_Clk code option The external clock signal is input from XIN pin XOUT pin is general purpose I O pin MCU VCC GND VSS VDD XIN XOUT Ext...

Page 53: ...00 35 00 40 00 45 00 2 1 2 5 3 3 1 3 3 3 5 4 4 5 5 5 5 6 6 5 7 VDD V Freq KHz ILRC The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD Flosc Internal low RC os...

Page 54: ...cle Fcpu This way is useful in RC mode Example Fcpu instruction cycle of external oscillator B0BSET P0M 0 Set P0 0 to be output mode for outputting Fcpu toggle signal B0BSET P0 0 Output Fcpu toggle si...

Page 55: ...SN8P2711A 8 Bit Micro Controller SONiX TECHNOLOGY CO LTD Page 55 Version 0 1...

Page 56: ...l Reset Circuit Active System Mode Switching Diagram Operating mode description MODE NORMAL SLOW GREEN POWER DOWN SLEEP REMARK EHOSC Running By STPHX By STPHX Stop IHRC Running By STPHX By STPHX Stop...

Page 57: ...or is still running B0BCLR FCLKMD To set CLKMD 0 Example Switch slow mode to normal mode The external high speed oscillator stops If external high clock stop and program want to switch back normal mod...

Page 58: ...N To disable TC0 interrupt service B0BCLR FTC0IRQ To clear TC0 interrupt request B0BSET FTC0GN To enable TC0 timer wake up function B0BSET FTC0ENB To enable TC0 timer Go into green mode B0BCLR FCPUM0...

Page 59: ...ME When the system is in power down mode sleep mode the high clock oscillator stops When waked up from power down mode MCU waits for 2048 external high speed oscillator clocks as the wakeup time to st...

Page 60: ...de Once interrupt service is executed the GIE bit in STKP register will clear to 0 for stopping other interrupt request On the contrast when interrupt service exits the GIE bit will set to 1 to accept...

Page 61: ...tion RETI is executed 0C9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTEN ADCIEN TC1IEN TC0IEN P01IEN P00IEN Read Write R W R W R W R W R W After reset 0 0 0 0 0 Bit 0 P00IEN External P0 0 inte...

Page 62: ...corresponding of the interrupt request 0C8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTRQ ADCIRQ TC1IRQ TC0IRQ P01IRQ P00IRQ Read Write R W R W R W R W R W After reset 0 0 0 0 0 Bit 0 P00IRQ...

Page 63: ...pt requests occurs and the program counter PC points to the interrupt vector ORG 8 and the stack add 1 level 0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKP GIE STKPB2 STKPB1 STKPB0 Read Wri...

Page 64: ...n save and load ACC PFLAG data into buffers and avoid main routine error after interrupt service routine finishing Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP buffer is...

Page 65: ...e INT0 interrupt request flag INT0IRQ is latched while system wake up from power down mode or green mode by P0 0 wake up trigger System inserts to interrupt vector ORG 8 after wake up immediately Note...

Page 66: ...ne ORG 8 Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers B0BTS1 FP00IRQ Check P00IRQ JMP EXIT_INT P00IRQ 0 exit interrupt vector B0BCLR FP00IRQ Reset P00IRQ...

Page 67: ...direction the INT1 interrupt request flag INT1IRQ is latched while system wake up from power down mode or green mode by P0 1 wake up trigger System inserts to interrupt vector ORG 8 after wake up imme...

Page 68: ...le TC0 interrupt request setup B0BCLR FTC0IEN Disable TC0 interrupt service B0BCLR FTC0ENB Disable TC0 timer MOV A 20H B0MOV TC0M A Set TC0 clock Fcpu 64 MOV A 74H Set TC0C initial value 74H B0MOV TC0...

Page 69: ...le TC1 interrupt request setup B0BCLR FTC1IEN Disable TC1 interrupt service B0BCLR FTC1ENB Disable TC1 timer MOV A 20H B0MOV TC1M A Set TC1 clock Fcpu 64 MOV A 74H Set TC1C initial value 74H B0MOV TC1...

Page 70: ...SN8P2711A 8 Bit Micro Controller SONiX TECHNOLOGY CO LTD Page 70 Version 0 1...

Page 71: ...lti interrupt situation Example ADC interrupt request setup B0BCLR FADCIEN Disable ADC interrupt service MOV A 10110000B B0MOV ADM A Enable P4 0 ADC input and ADC function MOV A 00000000B Set ADC conv...

Page 72: ...eck interrupt control bit and interrupt request flag in interrupt routine Example Check the interrupt request under multi interrupt operation ORG 8 Interrupt vector JMP INT_SERVICE INT_SERVICE Push ro...

Page 73: ...M P42M P40M Read Write R W R W R W R W R W After reset 0 0 0 0 0 0C5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5M P54M P53M Read Write R W R W After reset 0 0 Bit 7 0 PnM 7 0 Pn mode control b...

Page 74: ...0 0E4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4UR P44R P43R P42R P41R P40R Read Write W W W W W After reset 0 0 0 0 0 0E5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5UR P54R P53R Rea...

Page 75: ...0 0 0 0 0D5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5 P54 P53 Read Write R W R W After reset 0 0 Note The P04 keeps 1 when external reset enable by code option Example Read data from input...

Page 76: ...P4CON0 Read Write R W R W R W R W R W After reset 0 0 0 0 0 Bit 4 0 P4CON 4 0 P4 n configuration control bits 0 P4 n can be an analog input ADC input or digital I O pins 1 P4 n is pure analog input ca...

Page 77: ...able P4 1 digital function Enable P4 1 input mode B0BCLR P4M 1 Set P4 1 as input mode Example Set P4 1 to be general purpose output P4CON 1 must be set as 0 Check GCHS and CHS 2 0 status B0BCLR FGCHS...

Page 78: ...FH EVHENB VHS1 VHS0 Read Write R W R W R W After reset 0 0 0 Bit 7 EVHENB External ADC high reference voltage input control bit 0 Disable ADC external high reference voltage input 1 Enable ADC externa...

Page 79: ...sable external ADC high reference input EVHENB 0 execute next routine Check GCHS and CHS 2 0 status B0BCLR FGCHS If CHS 2 0 point to P4 0 CHS 2 0 000B set GCHS 0 If CHS 2 0 don t point to P4 0 CHS 2 0...

Page 80: ...scillator sec VDD Internal Low RC Freq Watchdog Overflow Time 3V 16KHz 512ms 5V 32KHz 256ms Note If watchdog is Always_On mode it keeps running event under power down mode or green mode Watchdog clear...

Page 81: ...timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Example An operation of watchdog timer is as following To clear the watchdog tim...

Page 82: ...SN8P2711A 8 Bit Micro Controller SONiX TECHNOLOGY CO LTD Page 82 Version 0 1...

Page 83: ...is 0xFF to 0X00 normally Under PWM mode TC0 overflow is decided by PWM cycle controlled by ALOAD0 and TC0OUT bits The main purposes of the TC0 timer is as following 8 bit programmable up counting tim...

Page 84: ...able P5 4 is output TC0OUT signal Bit 2 ALOAD0 Auto reload control bit Only valid when PWM0OUT 0 0 Disable TC0 auto reload function 1 Enable TC0 auto reload function Bit 3 TC0CKS TC0 clock source sele...

Page 85: ...rite R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 The equation of TC0C initial value is as following TC0C initial value N TC0 interrupt interval time input clock N is TC0 overflow bound...

Page 86: ...4000 ms 15625 us 010 Fcpu 64 16 384 ms 64 us 2000 ms 7812 5 us 011 Fcpu 32 8 192 ms 32 us 1000 ms 3906 25 us 100 Fcpu 16 4 096 ms 16 us 500 ms 1953 125 us 101 Fcpu 8 2 048 ms 8 us 250 ms 976 563 us 11...

Page 87: ...e N TC0 interrupt interval time input clock N is TC0 overflow boundary number TC0 timer overflow time has six types TC0 timer TC0 event counter TC0 Fcpu clock source TC0 Fosc clock source PWM mode and...

Page 88: ...eform is as following 1 2 3 4 1 2 3 4 TC0 Overflow Clock TC0OUT Buzzer Output Clock Example Setup TC0OUT output from TC0 to TC0OUT P5 4 The external high speed clock is 4MHz The TC0OUT frequency is 0...

Page 89: ...BSET FTC0CKS Select TC0 external clock source Select TC0 Fcpu Fosc internal clock source B0BCLR FTC0X8 Select TC0 Fcpu internal clock source or B0BSET FTC0X8 Select TC0 Fosc internal clock source Note...

Page 90: ...n 0 1 Set TC0 timer function mode B0BSET FTC0IEN Enable TC0 interrupt function or B0BSET FTC0OUT Enable TC0OUT Buzzer function or B0BSET FPWM0OUT Enable PWM function or B0BSET FTC0GN Enable TC0 green...

Page 91: ...rrupt to request interrupt service TC1 overflow time is 0xFF to 0X00 normally Under PWM mode TC1 overflow is decided by PWM cycle controlled by ALOAD1 and TC1OUT bits The main purposes of the TC1 time...

Page 92: ...ck source select bit 0 Internal clock Fcpu or Fosc 1 External clock from P0 1 INT1 pin Bit 6 4 TC1RATE 2 0 TC1 internal clock select bits TC1RATE 2 0 TC1X8 0 TC1X8 1 000 Fcpu 256 Fosc 128 001 Fcpu 128...

Page 93: ...00 0xFF 00000000b 11111111b Overflow per 256 count 1 0 0 256 0x00 0xFF 00000000b 11111111b Overflow per 256 count 1 0 1 64 0x00 0x3F xx000000b xx111111b Overflow per 64 count 1 1 0 32 0x00 0x1F xxx000...

Page 94: ...125 us 101 Fcpu 8 2 048 ms 8 us 250 ms 976 563 us 110 Fcpu 4 1 024 ms 4 us 125 ms 488 281 us 111 Fcpu 2 0 512 ms 2 us 62 5 ms 244 141 us The basic timer table interval time of TC1 TC1X8 1 High speed...

Page 95: ...e N TC1 interrupt interval time input clock N is TC1 overflow boundary number TC1 timer overflow time has six types TC1 timer TC1 event counter TC1 Fcpu clock source TC1 Fosc clock source PWM mode and...

Page 96: ...eform is as following 1 2 3 4 1 2 3 4 TC1 Overflow Clock TC1OUT Buzzer Output Clock Example Setup TC1OUT output from TC1 to TC1OUT P5 3 The external high speed clock is 4MHz The TC1OUT frequency is 0...

Page 97: ...TC1CKS Select TC1 external clock source Select TC1 Fcpu Fosc internal clock source B0BCLR FTC1X8 Select TC1 Fcpu internal clock source or B0BSET FTC1X8 Select TC1 Fosc internal clock source Note TC1X8...

Page 98: ...NOLOGY CO LTD Page 98 Version 0 1 Set TC1 timer function mode B0BSET FTC1IEN Enable TC1 interrupt function or B0BSET FTC1OUT Enable TC1OUT Buzzer function or B0BSET FPWM1OUT Enable PWM function Enable...

Page 99: ...ange the PWM s duty cycle is to modify the TCnR Note The n of TCn TCnC is 0 or 1 follow timer mode n 0 is TC0 mode n 1 is TC1 mode Note TCn is double buffer design Modifying TCnR to change PWM duty by...

Page 100: ...y range From following diagram the TCnIRQ frequency is related with PWM duty TCn Overflow TCnIRQ 1 PWMn Output Duty Range 0 15 0xFF TCnC Value 0x00 PWMn Output Duty Range 0 31 0xFF TCnC Value 0x00 PWM...

Page 101: ...CnC overflow PWM output High when TCnC TCnR PWM output Low If TCnR is changing in the program processing the PWM waveform will became as following diagram 1 1st PWM 2 Update PWM Duty 3 2nd PWM 4 Updat...

Page 102: ...MOV TC0M A Set the TC0 rate to Fcpu 4 MOV A 30 Set the PWM duty to 30 256 B0MOV TC0C A B0MOV TC0R A B0BCLR FTC0OUT Set duty range as 0 256 255 256 B0BCLR FALOAD0 B0BSET FPWM0OUT Enable PWM0 output to...

Page 103: ...with 4096 step resolution to transfer analog signal into 12 bits digital data The sequence of ADC operation is to select input source AIN0 AIN5 at first then set GCHS and ADS bit to 1 to start conver...

Page 104: ...obal channel select bit 0 Disable AIN channel 1 Enable AIN channel Bit 2 0 CHS 2 0 ADC input channels select bit 000 AIN0 001 AIN1 010 AIN2 011 AIN3 100 AIN4 101 AIN5 The AIN5 is internal 1 4 VDD inpu...

Page 105: ...1 Bit 0 ADR ADCKS1 ADCKS0 ADB3 ADB2 ADB1 ADB0 Read Write R W R W R R R R After reset 0 0 Bit 6 4 ADCKS1 ADCKS0 ADC clock source selection ADCKS1 ADCKS0 ADC Clock Source 0 0 Fcpu 16 0 1 Fcpu 8 1 0 Fcpu...

Page 106: ...ADB s output data AIN n ADB1 1 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 ADB3 ADB2 ADB1 ADB0 0 4096 VREFH 0 0 0 0 0 0 0 0 0 0 0 0 1 4096 VREFH 0 0 0 0 0 0 0 0 0 0 0 1 4094 4096 VREFH 1 1 1 1 1 1 1 1 1 1 1 0...

Page 107: ...if users connect more than one analog input signal to port 4 will encounter above current leakage situation P4CON is Port4 Configuration register Write 1 into P4CON 7 0 will configure related port 4...

Page 108: ...Note a ADC resolution is 8 bit if use internal 4V 3V 2V reference voltage b ADC resolution is 12 bit if use Internal VDD reference voltage or use external reference voltage 0AFH Bit 7 Bit 6 Bit 5 Bit...

Page 109: ...MHz 2 16 4 x16 512 us 0 1 Fcpu 8 1 4MHz 2 8 4 x16 256 us 1 0 Fcpu 1 4MHz 2 1 4 x16 32 us Fosc 2 1 1 Fcpu 2 1 4MHz 2 2 4 x16 64 us 0 0 Fcpu 16 1 4MHz 4 16 4 x16 1024 us 0 1 Fcpu 8 1 4MHz 4 8 4 x16 512...

Page 110: ...resistor B0BCLR FP40M Set P4 0 as input pin or MOV A 01H B0MOV P4CON A Set P4 0 as pure analog input Set VREFH is internal 3 0V MOV A 01H B0MOV VREFH A Set internal 3 0V VREFH Set ADC clock source Fc...

Page 111: ...og input Set VREFH is external input voltage B0BSET EVHENB Enable external VREFH input Set ADC clock source Fcpu MOV A 40H B0MOV ADR A To set ADC clock Fcpu Enable AIN0 P4 1 MOV A 91H B0MOV ADM A To e...

Page 112: ...ry to stable analog signal MCU VCC GND VREFH AINn P4 n VDD VSS 0 1uF Analog Signal Input 47uF 0 1uF ADC reference high voltage is from VDD pin and AIN0 P4 0 is VERFH input The VERFH should be from MCU...

Page 113: ...xor M 1 XOR M A M A xor M 1 N XOR A I A A xor I 1 SWAP M A b3 b0 b7 b4 M b7 b4 b3 b0 1 P SWAPM M M b3 b0 b7 b4 M b7 b4 b3 b0 1 N R RRC M A RRC M 1 O RRCM M M RRC M 1 N C RLC M A RLC M 1 E RLCM M M RL...

Page 114: ...Vop Vdd 0 5V 8 12 sink current IoL Vop Vss 0 5V 8 15 mA INTn trigger pulse width Tint0 INT0 interrupt request pulse width 2 fcpu cycle Vdd 5V 4Mhz 2 5 5 mA Idd1 Run Mode No loading Fcpu Fosc 4 Vdd 3V...

Page 115: ...INL VDD 5 0V AVREFH 3 2V FADSMP 7 8K 2 4 16 LSB No Missing Code NMC VDD 5 0V AVREFH 3 2V FADSMP 7 8K 8 10 12 Bits These parameters are for design reference not tested Internal 16MHz Oscillator RC Type...

Page 116: ...C Typical Power Voltage VDD 5V Typical Machin Cycle Fcpu Fhosc 4 Typical Internal 16MHz Oscillator RC Type Frequency 16MHz Testing Power Voltage Range VDD 3V 5 5V Testing Machine Cycle Range Fcpu Fho...

Page 117: ...RITER z Easy Writer V1 0 OTP programming is controlled by ICE without firmware upgrade suffers Please refer easy writer user manual for detailed information In SN8P2711A OTP programming by Easy Writer...

Page 118: ...age and LVD 2 4V 3 6V selection circuits CON1 I O port and ADC reference input Connect to SN8ICE 2K CON1 JP6 LVD 2 4V 3 6V input pins Connect to SN8ICE 2K JP6 S14 LVD 2 4V 3 6V control switch To emula...

Page 119: ...make J3 voltage 4 0V VDD R32 600 INT_VREFH VIN U2 LM431 VREFH V40 V20 INT_VREFH_TP C8 10uF R33 1K VIN INT_VREFH INT_VREFH R27 100 V20 VREFH VERFH VIN R31 200 VREFH V30 VREFH_TP S16 OFF ON 1 2 3 4 5 6...

Page 120: ...Y CO LTD Page 120 Version 0 1 12 4 2 SN8P2711 EV KIT CONNECT TO SN8ICE 2K The connection from SN8P2711 EV KIT to SN8ICE 2K is as following The ADC reference voltage is supplied by SN8P2711 EV KIT The...

Page 121: ...ING 12 5 1 SN8P2711 V3 TRANSITION BOARD SN8P2711 V3 transition board is for SN8P2711A OTP programming including P DIP 14 pin SOP 14 pin and SSOP 16 pin sockets connection JP2 Connect to EZ or EZ_MP wr...

Page 122: ...122 Version 0 1 U3 Set SSOP 16 pin socket for SN8P2711AX programming using SSOP 20 pin socket TX SSOP20PIN 12 5 2 SN8P2711 MP028A TRANSITION BOARD FOR EZ MPEZ WRITER SN8P2711 MP028A transition board...

Page 123: ...SN8P2711A 8 Bit Micro Controller SONiX TECHNOLOGY CO LTD Page 123 Version 0 1 12 5 3 SN8P2711 MP028A CONNECT TO EZ_MP WRITER 12 5 4 SN8P2711 MP028A CONNECT TO EZ WRITER...

Page 124: ...SN8P2711A 8 Bit Micro Controller SONiX TECHNOLOGY CO LTD Page 124 Version 0 1 12 5 5 SN8P2711 V3 CONNECT TO EZ WRITER 12 5 6 SN8P2711 V3 CONNECT TO EZ_MP WRITER...

Page 125: ...DIP4 4 45 DIP45 D2 10 9 D3 DIP5 5 44 DIP44 D4 12 11 D5 DIP6 6 43 DIP43 D6 14 13 D7 DIP7 7 42 DIP42 VPP 16 15 VDD DIP8 8 41 DIP41 RST 18 17 HLS DIP9 9 40 DIP40 ALSB PDB 20 19 DIP10 10 39 DIP39 DIP11 1...

Page 126: ...ssigment Number Name Number Pin Number Pin 1 VDD 1 VDD 1 VDD 2 GND 14 VSS 16 VSS 3 CLK 9 P4 0 11 P4 0 4 CE 5 PGM 13 P4 4 15 P4 4 6 OE 10 P4 1 12 P4 1 7 D1 8 D0 9 D3 10 D2 11 D5 12 D4 13 D7 14 D6 15 VD...

Page 127: ...13 1 P DIP 14 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 125 0 130 0 135 3 175 3 302 3 429 D 0 735 0 075 0 775 18 669 1 905 19 685 E 0 300 7 62 E1 0 245 0 250 0 255...

Page 128: ...m A 0 058 0 064 0 068 1 4732 1 6256 1 7272 A1 0 004 0 010 0 1016 0 254 B 0 013 0 016 0 020 0 3302 0 4064 0 508 C 0 0075 0 008 0 0098 0 1905 0 2032 0 2490 D 0 336 0 341 0 344 8 5344 8 6614 8 7376 E 0 1...

Page 129: ...mm A 0 053 0 069 1 3462 1 7526 A1 0 004 0 010 0 1016 0 254 A2 0 059 1 4986 b 0 008 0 012 0 2032 0 3048 b1 0 008 0 011 0 2032 0 2794 c 0 007 0 010 0 1778 0 254 c1 0 007 0 009 0 1778 0 2286 D 0 189 0 1...

Page 130: ...on line This note listed the production definition of all 8 bit MCU for order or obtain information This definition is only for Blank OTP MCU 14 2 MARKING INDETIFICATION SYSTEM SN8 X PART No X X X Tit...

Page 131: ...e Package Temperature Material SN8P2711APB OTP 2711A P DIP 0 70 PB Free Package SN8P2711ASB OTP 2711A SOP 0 70 PB Free Package 14 4 DATECODE SYSTEM X X X X XXXXX Year Month 1 January 2 February 9 Sept...

Page 132: ...yer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distributors harmless...

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