120
Section 6
Diagrams
Overall
Overall (1/3)
LENS
BI-371
IC 6011
C M O S
IM AG ER
DPR-394 (1/3)
C IS0_SI/SO /SC K
SD A/SC K/SD O
ISR X_D 0P/P0N _ISR X_D 07P/D 07N
CR -53
ND
IC 501,IC 701
C PLD
(M IPI to
LVD S)
D O P00-07/D O M 00-07
IC 6300
C AM ER A
SIG N AL
PR O C ES S
LEO _M IPID PH Y_0_TXC KP /TXC KN
LEO _M IPID PH Y_0_TXD P0-3
LEO _M IPID PH Y_0_TXDN 0-3
LEO _M IPID PH Y_1_TXC KP /TXC K N
LEO _M IPID PH Y_1_TXD P0-3
LEO _M IPID PH Y_1_TXDN 0-3
IC 1001
(M LL)2(D FE)_LVD S_C LK_P/N
(M LL)2(D FE)_LVD S_D P[1]-D P[7]
(M LL)2(D FE)_LVD S_DN [1]-DN [7]
(D FE)2(R O SE )_G C S2_00_P/N -
(D FE)2(R O SE )_G C S2_07_P/N
IC 2001(1/2)
CPU,
CAM ERA DSP,
VIDEO I/F,
M O DE CO NTRO L,
HD M I PRO CESS
IC 6501
N D
I/F
(D FE)2(M IPI)_
D T[0]-[23]
(D FE)_(M IPI)_
SD A/SC L
BO N O BO _SC K/SI/SO ,
XC S_BO N O BO
C M R _PI_O N ,
C M R _DR V1/2
(AS T)2(C M R )_SIO 2_SC K/SC S,
(AS T)2(C M R )_SIO 2_TXD ,
(C M R )2(AS T)_SIO 2_R XD
(D FE)2(AS T)_M IPI_D 0P/D 0N
(D FE)2(AS T)_M IPI_D 01P/D 1N
(D FE)2(AS T)_M IPI_D 02P/D 2N
(D FE)2(AS T)_M IPI_C KP /C KN
(D FE)2(M IPI)_D T[0]-[23]
(AS T)_(D FE)_H B_ADDR [00]-[19]
(AS T)2(LEN S)_U AR T1_TXD ,(LEN S)2(AS T)_U AR T1_R XD
(AS T)2(C M R )_C M R _PI_O N ,
(AS T)2(BN B3)_C M R _DR V1/2
IC 1801
M IPI
PH Y
C M R _PI_1/2
C M R _DR V_O U T_A/B
IC 6509,IC 6511,
IC 6512,IC 6519,
IC 6521,IC 6522
TR D ET
DR IVE R
IC 8402
D AC ,
H EA D PH O N E/
SP AM P
KS W -72(1/2)
(R O SE )2(G LEE )_
SIO _C LK/C S/SD O
(R O SE )2(G LEE )_SIO _
C LK/C S/SD O
H P_L_O U T
H P_R _O U T
SP +/-
H P_JAC K_IN
H P_L_O U T
H P_R _O U T
SPEAKE R
HP-181
H P JAC K
DIF-278 (1/3)
IC 1000
AUD IO
D SP
(AD SP )2
(G LEE )_SD O
(R O SE )2(AR IF)_
H IF_C LK
C M R _PI_O N
(AR IF)_(AUD SP )
_HD 1-HD 13
(R O SE )_H IF_C LK
AU _IN _A
M ICR O PH O N E
UN IT
IC 0700
FPG A
(C PU I/F)
(XLR )2(AR IF)_
I2S_D ATA
AU _XLR _
+1/-1,
AU _XLR _
+2/-2
AUDIO INPUT1
AUDIO INPUT2
(SW )2(AR IF)_SE L0/1_CH 1,
(SW )2(AR IF)_SE L0/1_CH 2
AS W -69
(SW )2(AR IF)_
SE L0/1_CH 1/CH 2
(XLR )2(AR IF)_I2S_D ATA
(SW )2(AR IF)_SE L0/1_CH 1,
(SW )2(AR IF)_SE L0/1_CH 2
IN PU T1/2
(LIN E/M IC /M IC +48V)
IC 2004
IC 2005
M IC
AM P
IC 2001
O P
AM P
IC 2003
AD C
AX M -62
IC 1303
AD C
IC 1302
M IC
AM P
(IN T)2(AR IF)_
I2S_D ATA
(AR IF)2(AD SP )_
SP I_C LK/XD S/M O SI
(R O SE )2(AR IF)_H IF_C LK
(R O SE )2(ETC B)_M O N I_2_TX0_P/N
(R O SE )2(ETC B)_M O N I_2_TX1_P/N
(R O SE )2(ETC B)_M O N I_3_TX0_P/N
(R O SE )2(ETC B)_M O N I_3_TX1_P/N
(R O SE )2(ETC )_M O N I_2_TX0_P/N
(R O SE )2(ETC )_M O N I_2_TX1_P/N
(R O SE )2(ETC )_M O N I_3_TX0_P/N
(R O SE )2(ETC )_M O N I_3_TX1_P/N
XDC A-FX9(BO B)
(R O SE )_H IF_C S0_X
(R O SE )_H IF_C S1_X
(R O SE )_H IF_C S2_X
(R O SE )_H IF_C S3_X
IC 7501
C PLD
(VU P4)
(R O SE )2(LCD )_R 2-R 9
(R O SE )2(LCD )_G 2-G 9
(R O SE )2(LCD )_B2-B9
(R O SE )_(VIN E)_I2C _SD A/SC L
IC 6000(1/3)
CN2001
CN1401(1/2)
CN2002
J001
HN -449
FP-310
G P-101 9
G Z9570 0
CO NTRO L SW ITCH
BLO CK
ZOO M /2nd SS
IF-137 7
HC -54
MULTI
INTERFACE
SHOE
(SH O E_D IG ITAL)2(AR IF)_
I2S_D ATA,
(SH O E_D IG ITAL)2(AR IF)_
I2S_D T34
(SH O E_D IG ITAL)2(AR IF)_
I2S_D ATA,
(SH O E_D IG ITAL)2(AR IF)
_I2S_D T34
(SH O E_D IG ITAL)2(AR IF)_
I2S_D T12,
(SH O E_D IG ITAL)2(AR IF)_
I2S_D T34
(2ND _ZOO M )2(AS T),
R EC _TR IG _2
(2ND _ZOO M )2(AS T),
R EC _TR IG _2
(KEY )2(AS T)_R EC _TR IG
(2ND _ZOO M )2(AS T),
R EC _TR IG _2
2ND _ZOO M /SS
(SH O E_D IG ITAL)2
(AR IF)_I2S_D T12,
(SH O E_D IG ITAL)2
(AR IF)_I2S_D T34
(AS T)2(SH O E)_U AR T3_TXD ,
(SH O E)2(AS T)_U AR T3_R XD
(AS T)2(SH O E)_U AR T3_TXD ,
(SH O E)2(AS T)_U AR T3_R XD
(SH O E_U AR T_TXD /R XD
(SH O E_U AR T_TXD /R XD
G PS _U AR T_TXD /R XD
G PS _U AR T_TXD /R XD
(AS T)2(G PS )_U AR T2_TXD ,
(G PS )2(AS T)_U AR T2_R XD
G PS
IN TER FACE
IC 7502
G PS
AN TEN NA
X7501
16.388M Hz
G PS _U AR T_
TXD /R XD
S2001
S2002
VID EO /AUD IO I/F,
I/O EXPA ND ER
C O D EC
(AS T)2(SH O E)_U AR T3_TXD ,
(SH O E)2(AS T)_U AR T3_R XD
(AS T)2(SH O E)_U AR T3_TXD ,
(SH O E)2(AS T)_U AR T3_R XD
(AS T)2(G PS )_U AR T2_R TS/(G PS )2(AS T)_U AR T2_R XD
(R O SE )2(FAN )_FAN _PW M
(FAN )2(R O SE )_FAN _FG
FR O M
D PR -394
BO ARD (2/3)
TO
D PR -394
BO ARD (3/3)
2
FR O M /TO
D PR -394
BO ARD (3/3)
1
FR O M /TO
D PR -394
BO ARD (3/3)
4
3
IC 1201-IC 1204
DDR 4
FPG A
(D FE SIG N AL
PR O C ESS )
FP -31 3
FP -31 9
F P -31 2
N D-
IN /O UT
ND _M +/M-
ND_UP/MID/LOW
CN 100
M
C M R 1A/B,C M R 2A/B
FR O M
D PR -394
BO ARD (1/3)
8
TO
CR -53
BO AR D
8
IC 2701
DDR 3
3
2
1
4
(SH O E)2(AS T)_SH O E_
ID 1/2/3
(SH O E)2(AS T)_SH O E_ID 1/2/3
(SH O E)2(AS T)_SH O E_ID 1/2/3
SH O E_ID 1/2/3_FR O N T
SH O E_ID 1/2/3
(SH O E)2(AS T)_SH O E_ID 1/2/3
SH O E_M IC _L/R
(SH O E)2(AR IF)
_I2S_D ATA
SH O E_
M IC _L/R
M IC
AM P
IC 3105
AD C
IC 3103
(SH O E)2(AR IF)_I2S_D ATA
(SH O E)2(AR IF)_I2S_D ATA
(SH O E1)2(AR IF)_I2S_D ATA
(KEY )2(R O SE )_R EC _TR IG
