12. Crystal, XO and Device Circuit Layout Recommendations
The following are recommendations for crystal layout (for devices that require an external reference), as well as device layout for all
variants. The main layout issues that should be carefully considered include the following:
• Number and size of the ground vias for the Epad
• Output clock trace routing
• Input clock trace routing
• Control and Status signals to input or output clock trace coupling
• Xtal signal coupling (external reference devices)
• Xtal layout (external reference devices)
If the application uses a crystal for the XAXB inputs a shield should be placed underneath the crystal connected to the X1 and X2 pins
to provide the best possible performance. The shield should not be connected to the ground plane(s), and the layers underneath should
have as little area under the shield as possible. It may be difficult to do this for all the layers, but it is important to do this for the layers
that are closest to the shield.
page to obtain Si5391 evaluation board schematics, layouts, and component BOM files.
12.1 64-Pin QFN Si5391/Si5391P Layout Recommendations
This section details the recommended guidelines for the external reference layout of the 64-pin Si5391/Si5391P device using an
example 8-layer PCB. The following are the descriptions of each of the eight layers.
• Layer 1: device layer, with low speed CMOS control/status signals
• Layer 2: crystal shield (applies to external reference devices only)
• Layer 3: ground plane
• Layer 4: power distribution
• Layer 5: power routing layer
• Layer 6: input clocks
• Layer 7: output clocks layer
• Layer 8: ground layer
The 64 pin QFN crystal guidelines show the top layer layout of the Si5391/Si5391P device mounted on the top PCB layer. This
particular layout was designed to implement either a crystal or an external oscillator as the XAXB reference. Note this applies only to
external reference devices. The crystal/ oscillator area is outlined with the white box around it. In this case, the top layer is flooded
with ground. Note that this layout has a resistor in series with each pin of the crystal. In typical applications, these resistors should be
removed.
12.1.1 Si5391 with an External Reference (Not Relevant to the Si5391P)
For devices that use an external reference like an XO, pins X1 and X2 should not be connected to "ground" and should be left as
"no-connects". An external reference does not need a crystal shield or the voids underneath the shield. The XA/XB connection should
be treated as a high speed critical path that is ac-coupled and terminated at the end of the etch run. The layout should minimize the
stray capacitance from the XA pin to the XB pin. Jitter is very critical at the XA/XB pins and therefore split termination and differential
signaling should be used whenever possible.
Si5391 Reference Manual • Crystal, XO and Device Circuit Layout Recommendations
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Rev. 0.5 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 11, 2022
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