For best jitter performance, use a XAXB frequency above 40 MHz. Also, for XAXB frequencies higher than 125 MHz, the PXAXB
control must be used to divide the input frequency down below 125 MHz.
In most applications, using the internal OSC with an external crystal provides the best phase noise performance. See
References; Optimizing Performance
for more information on the performance of various XO's with these devices.
The recommended crystal and oscillator suppliers are listed in the
Si534x/8x Jitter Attenuators Recommended Crystal, TCXO and
7.2.3 Clock Inputs on IN2, IN1, IN0
This section applies to all Si5391 devices except the Si5391P. The Si5391P cannot accept an input clock on IN0,1, 2.
A single ended or differential clock may be input to the IN2, 1, 0 inputs as shown below. All input signals must be ac-coupled. When
INx (x = 0, 1, 2) is unused and powered down the plus and minus input can be left floating. ClockBuilder Pro will power down any INx
input that is selected as “unused.” If any INx is powered up but does not have any input signal then the plus input should be left floating
and the minus input should be directly connected to ground. If the plus input is left floating and the minus input is connected to ground
with a 4.7 kΩ or smaller resistor, then the INx can be powered up or down when it does not have an input. The recommended input
termination schemes are shown in the figure below. Unused inputs can be disabled by register configuration.
50
100
INx
INxb
50
Standard AC-Coupled Differential
LVDS, LVPECL, CML
Standard AC-Coupled Single-Ended
INx
3.3V, 2.5V, 1.8V LVCMOS
R1
R
2
50
RS
RS matches the CMOS driver to a
50 ohm transmission line (if used)
C1
INxb
*This cap should have less than ~20 ohms of capacitive reactance at the clock input
frequency.
** Only when 3.3V LVCMOS driver is present, use R2 = 845 ohm and R1 = 267 ohm if
needed to keep the signal at INx < 3.6 Vpp_se. Including C1 = 6 pf may improve the
output jitter due to faster input slew rate at INx. If attenuation is not needed for
Inx<3.6Vppse, make R1 = 0 ohm and omit C1, R2 and the capacitor below R2. C1, R1,
and R2 should be physically placed as close as practicle to the device input pins.
0.1uF
*
0.1uF
*
* These caps should have < ~5 ohms capacitive reactance at the clock input frequency.
0.1uF
*
0.1uF
0.1uF
Clock IC
Standard
Clock IC
Standard
**
Figure 7.3. Terminations for Differential and Single-Ended Inputs
Si5391 Reference Manual • Clock Inputs
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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Rev. 0.5 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 11, 2022
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