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4.6.4 LVCMOS Output Polarity

When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUT and OUTb). By default the clock on
the OUTb pin is generated with the same polarity (in phase) with the clock on the OUT pin. The polarity of these clocks is configurable
enabling complementary clock generation and/or inverted polarity with respect to other output drivers. Note that these settings have no
effect on the differential-mode output driver.

Table 4.10. LVCMOS Output Polarity Registers

Register Name

Hex Address

[Bit Field]

Function

OUT0A_INV

0x0106[7:6]

Controls the output polarity of the OUT and
OUT pins when in LVCMOS mode. Selec-
tions are shown below in the table below.

OUT0_INV

0x010B[7:6]

OUT1_INV

0x0110[7:6]

OUT2_INV

0x0115[7:6]

OUT3_INV

0x011A[7:6]

OUT4_INV

0x011F[7:6]

OUT5_INV

0x0124[7:6]

OUT6_INV

0x0129[7:6]

OUT7_INV

0x012E[7:6]

OUT8_INV

0x0133[7:6]

OUT9_INV

0x0138[7:6]

OUT9A_INV

0x013D[7:6]

Table 4.11. LVCMOS Output Polarity of OUT and OUTb Pins

OUTx_INV

Register Settings

OUT

OUTb

Comment

0x00

CLK

CLK

Both in phase (default)

0x01

CLK

CLKb

Complementary

0x02

CLKb

CLKb

Both Inverted

0x03

CLKb

CLK

Inverted Complementary

Si5386 Rev. E Reference Manual • Output Clocks

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com

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Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 9, 2021

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Summary of Contents for Si5386

Page 1: ... Expectations with ClockBuilder Pro and the Register Map This reference manual is to be used to describe all the functions and features of the parts in the product family with register map details on how to implement them It is im portant to understand that the intent is for customers to use the ClockBuilder Pro soft ware to provide the initial configuration for the device Although the register ma...

Page 2: ...1 3 2 2 Use Case Scenario Using More Than Two Inputs 22 3 2 3 Hitless Input Switching with Phase Buildout 22 3 2 4 Ramped Input Switching 23 3 2 5 Hitless Switching Loss of Lock LOL and Fastlock 23 3 2 6 Glitchless Input Switching 23 3 2 7 Slew Rate Considerations 24 3 3 Fault Monitoring 25 3 3 1 Input Loss of Signal LOS Fault Detection 26 3 3 2 Out of Frequency OOF Detection 28 3 3 3 Loss of Lock...

Page 3: ...le Source Summary 50 4 8 Static Output Skew Control 51 4 9 Dynamic Output Skew Control 53 5 Zero Delay Mode 54 6 Serial Interface 56 6 1 I2C Interface 58 6 2 SPI Interface 60 7 Field Programming 65 8 XAXB External References 66 8 1 Performance of External References 66 9 XO and Device Circuit Layout Recommendations 67 9 1 Si5386 64 Pin QFN External XO Layout Recommendations 67 10 Power Management ...

Page 4: ... Page A Registers 119 12 9 Page B Registers 124 12 10 Page C Registers 129 13 Appendix Custom Differential Amplitude Controls 130 14 Revision History 132 Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 4 Rev 1 2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 9 2021 4 ...

Page 5: ...ng the ClockBuilder Pro software 1 2 LTE Frequency Configuration The device s frequency configuration is fully programmable through the serial interface and can also be stored in non volatile memory The flexible combination of dividers and a high frequency VCO allows the device to generate multiple output clock frequencies for applications that require ultra low phase noise and spurious performanc...

Page 6: ...8571 2457 6 2949 12 Note 1 R output dividers allow other frequencies to be generated These are useful for applications like JESD204B SYSREF clocks Si5386 Rev E Reference Manual Functional Description Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 6 Rev 1 2 Skyworks Proprietary Information Products and Product Information are Subject to Change W...

Page 7: ...requencies while the N1 N4 dividers generate the divided SYSREF used as the lower frequency frame clock Each output N divider also includes a configurable delay Δt for controlling deterministic latency This example shows a configuration where all the device clocks are controlled by a single delay Δt0 while the SYSREF clocks each have their own independent delay Δt1 Δt4 though other combinations ar...

Page 8: ...k time Higher Fastlock loop bandwidth settings will enable the DSPLLs to lock faster Fastlock Bandwidth settings up to 4 kHz are available for selection Fastlock bandwidth should generally be set from 10x to 100x the loop bandwidth for optimal results Once lock acquisition has completed the DSPLL s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting The Fastlock feature ca...

Page 9: ...tten to cause a newly written divider value to take effect Soft Reset All will also update the P divider values M DSPLL feedback divider 0x0515 0x051F 56 bit numerator 32 bit denominator Max value is 224 Fractional M divisors must be 10 Practical range limited by phase detector and VCO range The M divider has an update bit that must be written to cause a newly written divider value to take effect ...

Page 10: ...ut clocks available for selection Free Run Valid input clock selected Reset and Initialization Power Up Selected input clock fails Yes No Holdover History Valid Other Valid Clock Inputs Available No Yes Input Clock Switch VCO Freeze State An input is qualified and available for selection Figure 2 1 Modes of Operation Si5386 Rev E Reference Manual Modes of Operation Skyworks Solutions Inc Phone 781...

Page 11: ... 1 to this register bit performs the same func tion as power cycling the device All registers will be restored to their NVM values SOFT_RST 0x001C 0 Writing a 1 to this register bit performs a Soft Reset of the device Initiates register configuration changes without reloading NVM Power Up Serial interface ready RSTb pin asserted Hard Reset bit asserted Initialization NVM download Soft Reset bit as...

Page 12: ... the preamble and postamble write sequence when one of these registers is modified during device operation ClockBuilder Pro software adds these writes to the output file by default when Exporting Register Files 1 To start write the preamble by updating the following control bits using Read Modify Write sequences Register Value 0x0B24 0xC0 0x0B25 0x00 0x0540 0x01 2 Wait 625 ms for the device state ...

Page 13: ... Download register values with content stored in NVM DEVICE_READY 0x00FE 7 0 Indicates that the device is ready to accept com mands when value 0x0F 2 2 Free Run Mode Once power is applied to and initialization is complete the DSPLL will automatically enter Free run mode generating the output frequencies determined by the NVM The frequency accuracy of the generated output clocks in Free run mode is...

Page 14: ...e same as the holdover output frequency because the new input clock frequency might have changed and the holdover history circuit may have changed the holdover output frequency The ramp logic calculates the difference in frequency between the holdover frequency and the new desired output frequency Using the user selected ramp rate the correct ramp time is calculated The output ramp rate is then ap...

Page 15: ...LD_HIST_LEN 0x052E 4 0 Window Length time for historical average frequency used in Holdover mode Window Length in seconds s Window Length 2HOLD_HIST_LEN 1 x 8 3 x 10 7 HOLD_HIST_DELAY 0x052F 4 0 Delay Time to ignore data for historical average frequency in Holdover mode Delay Time in seconds s Delay Time 2HOLD_HIST_DELAY x 2 3 x 10 7 FORCE_HOLD 0x0535 0 Force the device into Holdover mode Used to ...

Page 16: ...between inputs or exiting holdover RAMP_STEP_SIZE 0x05A6 2 0 Size of the frequency ramp steps when ramping between inputs or exiting holdover 2 6 VCO Freeze Mode If holdover history is not valid the DSPLL automatically enters VCO Freeze mode when the selected input clock becomes invalid and no other valid input clocks are available for selection The DSPLL uses the last measured input frequency to ...

Page 17: ...3 1 1 Manual Input Switching In manual mode CLK_SWITCH_MODE 0x00 Input switching can be done manually using the IN_SEL 1 0 device pins from the package or through register 0x052A IN_SEL 2 1 Bit 0 of register 0x052A determines if the input selection is pin selectable or register selectable The default is pin selectable The following table describes the input selection on the pins Note that when Zer...

Page 18: ...ever tive 02 Automatic revertive 03 Reserved ZDM_EN 0x0487 0 0 disable zero delay mode 1 enable zero delay mode ZDM_AUTOSW_EN 0x0487 4 0 automatic switching disabled for zero delay mode 1 automatic input switching enabled and input clock selection governed by auto matic input switching engine IN0_PRIORITY 0x0538 2 0 IN0 IN1 IN2 IN3 priority select for the automatic selection state machine Priority...

Page 19: ...Ended INx 3 3 V 2 5 V 1 8 V LVCMOS R1 R2 50 RS RS matches the CMOS driver to a 50 ohm transmission line if used C1 INxb This cap should have less than 20 ohms of capacitive reactance at the clock input frequency Only when 3 3 V LVCMOS driver is present use R2 845 ohm and R1 267 ohm if needed to keep the signal at INx 3 6 Vpp_se Including C1 6 pf may improve the output jitter due to faster input sl...

Page 20: ... Clock IC Non Standard Or Pulsed CMOS Clock IC Attenuation circuit not required for 1 8 V input or if all input specifications in data sheet are met Attenuation circuit recommended but not required if input specifications in data sheet are met Figure 3 2 Input Terminations for DC Coupled Standard CMOS and Non Standard Pulsed CMOS Inputs Standard CMOS refers to a signal with a swing of 1 8 V 2 5 V ...

Page 21: ...ncluding the Standard AC Coupled Single Ended case In any of the CMOS modes it is not necessary to connect the inverting INx input pin To place the input buffer into any one of the CMOS modes the corresponding bit must be set in IN_PULSED_CMOS_EN 0x0949 7 4 Make sure the corresponding input bit is set to 1 for DC Coupled CMOS Mode Although the name is IN_PULSED_CMOS_EN this setting actually corres...

Page 22: ...ep 3 If the input points to a LOS input then set the input switch to manual mode Set CLK_SWITCH_MODE 1 0 0 Step 4 Change the input to an available active input Set IN_SEL 2 1 Set to 0 1 2 or 3 whichever is the available active input Step 5 Verify IN_ACTV to make sure the input is pointing to the active input as expected Step 6 Go back to automatic mode Set CLK_SWITCH_MODE 1 0 1 for Automatic non r...

Page 23: ...ed input switching and Ramped Exit from Holdover Table 3 7 Ramped Input Switching Control Registers Setting Name Hex Address Bit Field Function RAMP_STEP_INTERVAL 0x052C 7 5 Calculated by CBPro based on the selected ramp rate RAMP_STEP_SIZE 0x05A5 2 0 Calculated by CBPro based on the selected ramp rate RAMP_SWITCH_EN 0x05A6 3 Enable frequency ramping on an input switch HSW_MODE 0x053A 1 0 Input sw...

Page 24: ...It shows the relative increase in the amount of RMS jitter due to low slew rate and is not intended to show absolute jitter values 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 0 100 200 300 400 500 600 Relateive Jitter Input Slew V us IN_X Slew Rate in Differential Mode JTYP Figure 3 3 Effect of Low Input Slew Rate on Output RMS Jitter Si5386 Rev E Reference Manual Clock Inputs Skyworks Solutions Inc Phone 781...

Page 25: ...ted when the DSPLL loses synchronization with its reference input DSPLL LPF PD M IN0 IN0 Precision Fast OOF LOS P0 IN1 IN1 Precision Fast OOF LOS P1 IN3 FB_IN IN3 FB_IN Precision Fast OOF LOS P3 IN2 IN2 Precision Fast OOF LOS P2 LOL XB XA OSC LOS 5 Figure 3 4 Si5386 Fault Monitors Si5386 Rev E Reference Manual Clock Inputs Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksin...

Page 26: ...isabled when LOSXAXB is detected This feature can be disabled such that the device will continue to produce output clocks even when LOSXAXB is detected Single ended inputs must be connected to the XA input pin with the XB pin terminated properly for LOSXAXB to function correctly The table below lists the loss of signal status indicators and fault monitoring control registers Table 3 8 Loss of Sign...

Page 27: ...ngle period larger than this threshold will assert LOS A continuous run of periods that are less than this period and more than the minimum period set by LOS_CLR_THR will de assert LOS LOS_CLR_THR 0x0036 7 0 0x003D 7 0 Sets the minimum period at the output of the P divider for IN3 2 1 0 A single period smaller than this threshold will assert LOS A continuous run of periods that are greater than th...

Page 28: ...le OOF Reference Hysteresis Hysteresis OOF Declared OOF Cleared 6 ppm 4 ppm 0 ppm 4 ppm 6 ppm fIN Clear Set Clear Set Figure 3 8 Example of Precision OOF Monitor Assertion and De assertion Triggers The table below lists the OOF monitoring and control registers Because the precision OOF monitor needs to provide 1 16 ppm of frequency measurement accuracy it must measure the monitored input clock fre...

Page 29: ...old Range is up to 511 ppm in steps of 1 16 ppm OOF_CLR_THR 0x004A 7 0 0x004D 7 0 OOF Clear threshold Range is up to 511 ppm in steps of 1 16 ppm FAST_OOF_SET_THR 0x0051 7 0 0x0054 7 0 Determines the fast OOF alarm set threshold for IN3 IN2 IN1 IN0 FAST_OOF_CLR_THR 0x0055 7 0 0x0058 7 0 Determines the fast OOF alarm clear threshold for IN3 IN2 IN1 IN0 Si5386 Rev E Reference Manual Clock Inputs Sky...

Page 30: ...er always displays the current LOL state and a sticky register always stays asserted until cleared The LOL pin reflects the current state of the LOL monitor DSPLL LPF PD M LOL Clear LOL Set Timer LOLb LOS LOL Sticky Live LOL Monitor fIN Feedback Clock 5 Figure 3 9 Si5386 LOL Status Indicator The LOL frequency monitors have an adjustable sensitivity which is register configurable from 0 1 ppm to 10...

Page 31: ...er sets the delay value for the LOL clear delay timer Set by CBPro FASTLOCK_EXTEND_EN 0x00E5 5 Enables FASTLOCK_EXTEND FASTLOCK_EXTEND 0x00ED 4 0 0x00EC 7 0 0x00EB 7 0 0x00EA 7 0 Set by CBPro to minimize phase transients when switching the PLL bandwidth FASTLOCK_EXTEND_SCL 0x0294 7 4 Set by CBPro LOL_SLW_VALWIN_SELX 0x0296 1 Set by CBPro FASTLOCK_DLY_ONSW_EN 0x0297 1 Set by CBPro FASTLOCK_DLY_ONSW...

Page 32: ...LOL_FLG mask IN0_OOF_FLG mask IN0_LOS_FLG mask IN0 mask 0x0012 0 0x0012 4 0x0012 1 0x0012 5 0x0012 2 0x0012 6 0x0012 3 0x0012 7 0x0013 1 0x0013 5 0x0011 1 Register Bit Locations XAXB_LOS_FLG CAL_FLG_PLL INTR mask mask SYSINCL_FLG Figure 3 11 Interrupt Triggers and Masks The _FLG bits are sticky versions of the alarm bits and will stay high until cleared A _FLG bit can be cleared by writing a zero ...

Page 33: ...ther interrupt sources If LOS 0 is high then LOS_FLG 0 and the interrupt cannot be cleared Note that the INTR pin may toggle during reset Si5386 Rev E Reference Manual Clock Inputs Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 33 Rev 1 2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice Dece...

Page 34: ...le and can be stored in NVM so that the desired output configuration is ready at power up Any N divider can source multiple or even all output drivers N0 N1 N2 N3 N4 OUT2b VDDO2 OUT2 VDDO3 VDDO0 OUT0Ab OUT0A OUT0b OUT0 R2 R0A OUT3b OUT3 R3 OUT1b VDDO1 OUT1 R1 OUT5b VDDO5 OUT5 VDDO6 R5 OUT6b OUT6 R6 OUT4b VDDO4 OUT4 R4 OUT7b VDDO7 OUT7 VDDO8 R7 OUT8b OUT8 R8 VDDO9 OUT9b OUT9Ab OUT9A R9 R0 R9A OUT9 ...

Page 35: ...L 0x0138 2 0 OUT9A_MUX_SEL 0x013D 2 0 4 1 1 Output R Divider Synchronization The output R dividers can be reset to a known state by driving the SYNCb input pin low or by setting the SYNC register bit 0x001E 2 high Resetting the device using the Resetb pin or asserting the Hard Reset register bit 0x001E 1 will give the same result Soft Reset does not affect the output synchronization Si5386 Rev E R...

Page 36: ...are illustrated 1 Avoid adjacent frequency values that are close in frequency A 156 25 MHz clock should not be placed next to a 155 52 MHz clock as crosstalk will be observed at 0 73 MHz offset from each frequency If the jitter integration bandwidth or spur range goes up to 20 MHz then keep adjacent frequencies at least 20 MHz apart 2 Frequency values that are integer multiples of one another shou...

Page 37: ... format uses a low power format which has an output impedance that is much higher than 100 Ω In addition to supporting differential signals any of the outputs can be configured as LVCMOS 3 3 2 5 or 1 8 V drivers providing up to 24 single ended outputs or any combination of differential and single ended outputs Note also that CMOS output can create much more crosstalk than differential outputs so e...

Page 38: ...N 0x010B 3 Similar to OUT0A settings OUT0_VDD_SEL 0x010B 5 4 OUT1_VDD_SEL_EN 0x0110 3 OUT1_VDD_SEL 0x0110 5 4 OUT2_VDD_SEL_EN 0x0115 3 OUT2_VDD_SEL 0x0115 5 4 OUT3_VDD_SEL_EN 0x011A 3 OUT3_VDD_SEL 0x011A 5 4 OUT4_VDD_SEL_EN 0x011F 3 OUT4_VDD_SEL 0x011F 5 4 OUT5_VDD_SEL_EN 0x0124 3 OUT5_VDD_SEL 0x0124 5 4 OUT6_VDD_SEL_EN 0x0129 3 OUT6_VDD_SEL 0x0129 5 4 OUT7_VDD_SEL_EN 0x012E 3 OUT7_VDD_SEL 0x012E ...

Page 39: ... 2 5V 1 8 V LVCMOS VDDO 3 3V 2 5V 1 8V 50 Rs 50 Rs DC Coupled LVCMOS OUTx OUTxb VDDRX Standard HCSL Receiver R1 AC Coupled HCSL 50 50 50 3 3V 2 5V 1 8V VDDO OUTx OUTxb R1 R2 R2 VDDRX R1 R2 3 3V 2 5V 1 8V 442Ω 332Ω 243Ω 56 2Ω 59Ω 63 4Ω For VCM 0 35V Figure 4 2 Si5386 Supported Differential Output Terminations Si5386 Rev E Reference Manual Output Clocks Skyworks Solutions Inc Phone 781 376 3000 Fax ...

Page 40: ...PL 0x0105 6 4 Sets the voltage swing for the differential output drivers for both Normal and Low Power modes This field only applies when OUTx_FORMAT 1 or 2 OUT0_AMPL 0x010A 6 4 OUT1_ AMPL 0x010F 6 4 OUT2_ AMPL 0x0114 6 4 OUT3_ AMPL 0x0119 6 4 OUT4_ AMPL 0x011E 6 4 OUT5_ AMPL 0x0123 6 4 OUT6_ AMPL 0x0128 6 4 OUT7_ AMPL 0x012D 6 4 OUT8_ AMPL 0x0132 6 4 OUT9_ AMPL 0x0137 6 4 OUT9A_ AMPL 0x013C 6 4 S...

Page 41: ...t Common Mode Voltage Selection Registers Register Name Hex Address Bit Field Function OUT0A_CM 0x0105 3 0 Sets the common mode voltage for the differential output driver This field only ap plies when OUTx_FORMAT 1 or 2 OUT0_CM 0x010A 3 0 OUT1_ CM 0x010F 3 0 OUT2_ CM 0x0114 3 0 OUT3_ CM 0x0119 3 0 OUT4_ CM 0x011E 3 0 OUT5_ CM 0x0123 3 0 OUT6_ CM 0x0128 3 0 OUT7_ CM 0x012D 3 0 OUT8_ CM 0x0132 3 0 O...

Page 42: ... more detail in this appendix Table 4 7 Recommended Settings for Differential LVPECL LVDS HCSL and CML Standard VDDO Mode OUTx_FORMAT OUTx_CM OUTx_AMPL V Dec Dec Dec LVPECL 3 3 Normal 1 11 6 LVPECL 2 5 Normal 1 11 6 LVDS 3 3 Normal 1 3 3 LVDS 2 5 Normal 1 11 3 Sub LVDS1 1 8 Normal 1 13 3 HCSL2 3 3 Low Power 2 13 3 HCSL2 2 5 Low Power 2 10 3 HCSL2 1 8 Low Power 2 13 3 Note 1 The Sub LVDS common mod...

Page 43: ... 50 Rs 50 Rs DC Coupled LVCMOS OUTx OUTxb Figure 4 3 LVCMOS Output Terminations Si5386 Rev E Reference Manual Output Clocks Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 43 Rev 1 2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 9 2021 43 ...

Page 44: ...tages Table 4 9 LVCMOS Drive Strength Registers Register Name Hex Address Bit Field Function OUT0A_CMOS_DRV 0x0104 7 6 LVCMOS output impedance See the table above for settings OUT0_CMOS_DRV 0x0109 7 6 OUT1_ CMOS_DRV 0x010E 7 6 OUT2_ CMOS_DRV 0x0113 7 6 OUT3_ CMOS_DRV 0x0118 7 6 OUT4_ CMOS_DRV 0x011D 7 6 OUT5_ CMOS_DRV 0x0122 7 6 OUT6_ CMOS_DRV 0x0127 7 6 OUT7_ CMOS_DRV 0x012C 7 6 OUT8_ CMOS_DRV 0x...

Page 45: ...he OUT and OUT pins when in LVCMOS mode Selec tions are shown below in the table below OUT0_INV 0x010B 7 6 OUT1_INV 0x0110 7 6 OUT2_INV 0x0115 7 6 OUT3_INV 0x011A 7 6 OUT4_INV 0x011F 7 6 OUT5_INV 0x0124 7 6 OUT6_INV 0x0129 7 6 OUT7_INV 0x012E 7 6 OUT8_INV 0x0133 7 6 OUT9_INV 0x0138 7 6 OUT9A_INV 0x013D 7 6 Table 4 11 LVCMOS Output Polarity of OUT and OUTb Pins OUTx_INV Register Settings OUT OUTb C...

Page 46: ...lding the OEb pin low enables all of the outputs while driving it high disables all outputs In addition to pin control flexible register controls described in the following sections allow further customization for each application Note that any one disable control can disable the corresponding output s even if all other sources controls are enabled See the sections below especially 4 7 5 Output Dr...

Page 47: ... OUT0_DIS_STATE 0x0109 5 4 OUT1_ DIS_STATE 0x010E 5 4 OUT2_ DIS_STATE 0x0113 5 4 OUT3_ DIS_STATE 0x0118 5 4 OUT4_ DIS_STATE 0x011D 5 4 OUT5_ DIS_STATE 0x0122 5 4 OUT6_ DIS_STATE 0x0127 5 4 OUT7_ DIS_STATE 0x012C 5 4 OUT8_ DIS_STATE 0x0131 5 4 OUT9_ DIS_STATE 0x0136 5 4 OUT9A_ DIS_STATE 0x013B 5 4 Si5386 Rev E Reference Manual Output Clocks Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100...

Page 48: ...Synchronous output Enable Disable selec tion 0 Asynchronous Enable Disable default 1 Synchronous Enable Disable OUT0_SYNC_EN 0x0109 3 OUT1_ SYNC_EN 0x010E 3 OUT2_ SYNC_EN 0x0113 3 OUT3_ SYNC_EN 0x0118 3 OUT4_ SYNC_EN 0x011D 3 OUT5_ SYNC_EN 0x0122 3 OUT6_ SYNC_EN 0x0127 3 OUT7_ SYNC_EN 0x012C 3 OUT8_ SYNC_EN 0x0131 3 OUT9_ SYNC_EN 0x0136 3 OUT9A_SYNC_EN 0x013B 3 4 7 3 Automatic Output Disable Durin...

Page 49: ...LOL 0x0142 1 Determines if the outputs are disabled dur ing an LOL condition 0 Disable all outputs on LOL default 1 Normal Operation during LOL OUT_DIS_MSK_LOSXAXB 0x0141 6 Determines if outputs are disabled during an LOSXAXB condition 0 Disable all outputs on LOSXAXB de fault 1 All outputs remain enabled during LOS XAXB Si5386 Rev E Reference Manual Output Clocks Skyworks Solutions Inc Phone 781 ...

Page 50: ...e Related Registers bits Comments OUTALL_DISA BLE_LOW Low N N 0x0102 0 User Controllable OUT0A_OE OUT0_OE OUT1_OE OUT2_OE OUT3_OE OUT4_OE OUT5_OE OUT6_OE OUT7_OE OUT8_OE OUT9_OE OUT9A_OE Low Y N 0x0103 1 0x0108 1 0x010D 1 0x0112 1 0x0117 1 0x011C 1 0x0121 1 0x0126 1 0x012B 1 0x0130 1 0x0135 1 0x013A 1 User Controllable OEb pin High Y N 0x0022 1 0 User Controllable OE register Low LOL High N Y 0x00...

Page 51: ...onfigurable Path Delays A Soft Reset of the device SOFT_RST 0x001C 0 1 is required to latch in the new delay value s All delay values are restored to their NVM values after POR RSTb or HARD_RST Delay default values can be written to NVM allowing a custom delay offset configuration at power up or after a Hard Reset Two sets of registers control the static output to output skew Nx_DELAY and Nx_IODEL...

Page 52: ...T 15 0 0x0A52 7 0 0x0A51 7 0 N1_IODELAY_DEC_EN 0x0A53 1 N1_IODELAY_INC_EN 0x0A53 0 N2_IODELAY_STEP 7 0 0x0A54 N2_IODELAY_COUNT 15 0 0x0A56 7 0 0x0A55 7 0 N2_IODELAY_DEC_EN 0x0A57 1 N2_IODELAY_INC_EN 0x0A57 0 N3_IODELAY_STEP 7 0 0x0A58 N3_IODELAY_COUNT 15 0 0x0A5A 0x0A59 N3_IODELAY_DEC_EN 0x0A5B 1 N3_IODELAY_INC_EN 0x0A5B 0 N4_IODELAY_STEP 7 0 0x0A5C N4_IODELAY_COUNT 15 0 0x0A5E 0x0A5D N4_IODELAY_D...

Page 53: ...TEP 67 8 ps The direction of the delay ad justment is defined asserting either Nx_PHASE_INC or Nx_PHASE_DEC N0_COUNT_COUNT 15 0 0x0A3A 7 0 0x0A39 7 0 N0_PHASE_DEC 0x0A3B 1 N0_PHASE_INC 0x0A3B 0 N1_PHASE_STEP 7 0 0x0A3C N1_COUNT_COUNT 15 0 0x0A3E 7 0 0x0A3D 7 0 N1_PHASE_DEC 0x0A3F 1 N1_PHASE_INC 0x0A3F 0 N2_PHASE_STEP 7 0 0x0A40 N2_COUNT_COUNT 15 0 0x0A42 0x0A41 N2_PHASE_DEC 0x0A43 1 N2_PHASE_INC 0...

Page 54: ...should be made after this time expires or they will be overwritten with the NVM values A wait of 1000 ms is sufficient Contact Skyworks technical support for special register writes that can greatly reduce this wait time IN0 IN0b IN1 IN1b IN2 IN2b P1 P0 P2 DSPLL LPF PD M IN3 FB_IN P3 100 IN3b FB_INb N0 N1 N2 N3 N4 OUT2b VDDO2 OUT2 VDDO0 OUT0Ab OUT0A OUT0b OUT0 R2 R0A R0 VDDO8 OUT8b OUT8 R8 VDDO9 O...

Page 55: ...put Select control source 0 Pin controlled input clock selection default 1 ZDM_IN_SEL register input clock selection for ZDM Note 1 When ZDM_EN 1 and IN_SEL_REG_CTRL 1 the IN_SEL pins and register bits have no effect Table 5 2 Input Clock Selection in Zero Delay Mode ZDM_EN IN_SEL_REGCTRL Input Clock Selection Governed by 0 0 IN_SEL 1 0 Pins 0 1 IN_SEL Register 1 0 IN_SEL 1 0 Pins ZDM 1 1 ZDM_IN_S...

Page 56: ...L 0 digital I O in the NVM allows the host to reliably write the device regardless of its operating voltage Once the serial interface type has been chosen using the I2C_SEL pin the device may be written successfully regardless of the host interface type This is true for both 3 wire and 4 wire SPI modes as well as I2C The SPI serial data is written to the same SDA SDIO input pin in all cases At thi...

Page 57: ... 3 3 V digital I O connections SPI_3WIRE 0x002B 3 Selects operating mode for SPI interface 0 4 wire SPI default 1 3 wire SPI I2C_ADDR 0x000B 6 0 7 bit I2C Address See 6 1 I2C Interface for more information Si5386 Rev E Reference Manual Serial Interface Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 57 Rev 1 2 Skyworks Proprietary Information Pr...

Page 58: ...igure 6 3 7 bit I2C Slave Address Bit Configuration The I2C bus supports SDA timeout for compatibility with SMB Bus interfaces The error indicator and flag are listed in the registers listed in the table below Table 6 2 SMB Bus Timeout Error Registers Register Name Hex Address Bit Field Function SMBUS_TIMEOUT 0x000C 5 SMB Bus Timeout Indicator 0 SMB Bus Timeout has Not occurred 1 SMB Bus Timeout H...

Page 59: ...ration is also supported This is shown in the following figure 1 Read 0 Write A Acknowledge SDA LOW N Not Acknowledge SDA HIGH S START condition P STOP condition Read Operation Single Byte S 0 A Reg Addr 7 0 Slv Addr 6 0 A P Read Operation Burst Auto Address Increment Reg Addr 1 S 1 A Slv Addr 6 0 Data 7 0 P N S 0 A Reg Addr 7 0 Slv Addr 6 0 A P S 1 A Slv Addr 6 0 Data 7 0 A P N Data 7 0 Host Cloc...

Page 60: ...erminated by de asserting CSb CSb high 3 There is no limit to the number of data bytes that follow the Burst Write Command but the address will wrap around to zero in the byte after address 255 is written Writing or reading data consist of sending a Set Address command followed by a Write Data or Read Data command The Write Data Address Increment or Read Data Address Increment commands are availab...

Page 61: ...ment Set Address and Read Data Set Addr Addr 7 0 Read Data Data 7 0 Set Addr Addr 7 0 Read Data Data 7 0 Set Addr Addr 7 0 Read Data Data 7 0 Read Data Addr Inc Data 7 0 Read Data Addr Inc Data 7 0 Set Addr Addr 7 0 Read Data Addr Inc Data 7 0 Clock IC Host Clock IC Host Figure 6 8 Example of Reading Three Data Bytes Using the SPI Read Commands The timing diagrams for the SPI commands are shown in...

Page 62: ... 5 6 7 0 1 2 3 4 5 6 6 7 Clock IC Host Clock IC Host Don t Care High Impedance 7 7 Figure 6 9 SPI Set Address Command Timing Si5386 Rev E Reference Manual Serial Interface Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 62 Rev 1 2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 9 20...

Page 63: ...6 7 6 7 Clock IC Host Clock IC Host Don t Care High Impedance 1 9 SCLK Periods Figure 6 10 SPI Write Data and Write Data Address Increment Instruction Timing Si5386 Rev E Reference Manual Serial Interface Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 63 Rev 1 2 Skyworks Proprietary Information Products and Product Information are Subject to Ch...

Page 64: ...yte base address n 3 Wire Burst Data Write Command 2 Cycle Wait Previous Command SDI 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 Clock IC Host Clock IC Host Don t Care High Impedance 1st data byte base address 6 Next Command 6 7 7 7 7 7 7 7 1 9 SCLK Periods Figure 6 12 SPI Burst Data Write Instruction Timing Si5386 R...

Page 65: ...ogramming of Si5386 sample devices Refer to https www skyworksinc com en products timing evaluation kits general clockbuilder pro field pro grammer for information about this kit Si5386 Rev E Reference Manual Field Programming Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 65 Rev 1 2 Skyworks Proprietary Information Products and Product Informa...

Page 66: ... Figure 8 1 XA XB Input Place the XO as close to the XA XB pins as possible Also take special care that other signals are extremely well isolated from the XA XB input pins Because the R1 and R2 resistance in combination with the XA input capacitance forms a low pass filter the capacitor C1 is required to compensate for this and give a faster slew rate of the clock at XA For the LVCMOS XO connectio...

Page 67: ...und flooded Layer 2 input clocks ground flooded Layer 3 ground plane Layer 4 power distribution ground flooded Layer 5 power routing layer Layer 6 ground input clocks ground flooded Layer 7 output clocks layer Layer 8 ground layer External XO The figure below shows the top layer layout of the Si5386 device mounted on the PCB The XO is outlined with the white box around it The top layer is flooded ...

Page 68: ...ve a ground shield above below and on the sides for maximum protection Figure 9 2 External XO Input Clocks and Ground Fill Below the Top Layer Layer 2 Si5386 Rev E Reference Manual XO and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 68 Rev 1 2 Skyworks Proprietary Information Products and Product Informat...

Page 69: ...xternal XO Internal Ground Plane Layer 3 Figure 9 4 External XO Internal Power Plane Layer 4 Si5386 Rev E Reference Manual XO and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 69 Rev 1 2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 9 2021 6...

Page 70: ... another ground plane similar to layer 3 Figure 9 6 External XO Internal Ground Plane Layer 6 Si5386 Rev E Reference Manual XO and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 70 Rev 1 2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 9 2021 ...

Page 71: ...nd flood on either side of the output clocks to ensure that the ground flood immediately next to the differential pairs has a low inductance path to the ground plane on layers 3 and 6 Figure 9 7 External XO Output Clocks Layer 7 Si5386 Rev E Reference Manual XO and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc...

Page 72: ...XO Bottom Layer Ground Flooded Layer 8 Si5386 Rev E Reference Manual XO and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 72 Rev 1 2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 9 2021 72 ...

Page 73: ...Powers down all output drivers 0 Normal Operation default 1 Powerdown All output drivers IN_EN 0x0949 3 0 Enable or powerdown the IN3 IN0 input buffers 0 Powerdown input buffer 1 Enable and Power up input buffer 10 2 Power Supply Recommendations Power supply filtering is generally important for optimal timing performance The Si5386 devices have multiple stages of on chip regulation to minimize the...

Page 74: ...ow VDD until VDD itself is powered down This is due to the pad I O circuits which have large MOSFET switches to select the local supply from either the VDD or VDDA rails These devices are relatively large and yield a parasitic diode between VDD and VDDA Allow for both VDD and VDDA to power up and power down before measuring their respective voltages 10 4 Grounding Vias The Epad on the bottom of th...

Page 75: ...m all devices with custom orderable part number custom OPN Custom OPN devices contain all of the initialization information in their non volatile memory NVM so that it powers up fully configured and ready to go Because preprogrammed device applications are inherently quite different from one another the default power up values of the register settings can be determined using the custom OPN utility...

Page 76: ...lt Description 0x0002 7 0 R PN_BASE 0x86 Four digit base part num ber one nibble per digit Ex ample Si5386A E GM The base part number is 5386 which is stored in this regis ter 0x0003 15 8 R PN_BASE 0x53 See 11 3 Part Numbering Summary for more information on part numbers Table 12 4 Register 0x0004 Device Grade Reg Address Bit Field Type Name Description 0x0004 7 0 R GRADE One ASCII character indic...

Page 77: ...6 0 R I2C_ADDR 7 bit I2C Address Note that the two least significant bits 1 0 are determined by the voltages on the A1 and A0 input pins respectively This setting is not saved as part of the usual NVM write procedure To update this register in a non volatile way the Si534x8x I2C Address Burn Tool allows updating this value one time This utility is included in the ClockBuilder Pro installation and ...

Page 78: ...ld Type Name Description 0x000F 5 R CAL 1 if the DSPLL internal calibration is currently busy See 3 3 Fault Monitoring for more information Table 12 13 Register 0x0011 Device Status Flags Reg Address Bit Field Type Name Description 0x0011 0 R W SYSINCAL_FLG Flag 1 if the device was in SYSINCAL 0x0011 1 R W LOSXAXB_FLG Flag 1 if the XAXB reference clock showed LOS XAXB 0x0011 2 R W LOSREF_FLG Flag ...

Page 79: ...Register 0x0014 DSPLL Calibration Status Flag Reg Address Bit Field Type Name Description 0x0014 5 R W CAL_FLG Flag 1 if the internal calibration was or is busy These are sticky flag bits corresponding to the bits in register 0x000F They are cleared by writing 0 to the bit that has been set The corresponding 0x000F register bit must be 0 to clear this sticky flag bit See 3 3 Fault Monitoring for m...

Page 80: ...e bits in register 0x0013 For more information see Section 3 3 Fault Monitoring Table 12 20 Register 0x001A PLL In Calibration Interrupt Mask Reg Address Bit Field Type Name Description 0x001A 5 R W CAL_INTR_MSK 1 to mask CAL_FLG from causing an interrupt This is the interrupt mask bit corresponding to the bit in register 0x0014 For more information see Section 3 3 Fault Monitoring Table 12 21 Reg...

Page 81: ...isable 0x0022 1 R W OE_REG_DIS When OE_REG_SEL 1 0 Disable selected outputs 1 Enable selected outputs By default ClockBuilder Pro sets the OEb pin controlling all outputs OUTALL_DISABLE_LOW 0x0102 0 must be high enabled to allow the OEb pin to enable outputs Note that the OE_REG_DIS bit active high has inverted logic sense from the OEb pin active low See 4 7 5 Output Driver Disable Source Summary ...

Page 82: ...ust remain valid for this period of time before that clock is considered to be qualified again Table 12 27 Register 0x002E 0x002F IN0 LOS Trigger Threshold Reg Address Bit Field Type Name Description 0x002E 7 0 R W LOS0_TRG_THR 16 bit LOS Trigger Threshold value 0x002F 15 8 R W LOS0_TRG_THR ClockBuilder Pro calculates the correct LOS register threshold trigger value for IN0 given a particular freq...

Page 83: ...alues set by CBPro Table 12 31 Register 0x003F OOF Enable Reg Address Bit Field Type Name Description 0x003F 3 0 R W OOF_EN Enable Precision OOF for IN3 IN0 0 Disable Precision OOF 1 Enable Precision OOF 0x003F 7 4 R W FAST_OOF_EN Enable Fast OOF for IN3 IN0 0 Disable Fast OOF 1 Enable Fast OOF IN0 OOF_EN 0 FAST_OOF_EN 4 IN1 OOF_EN 1 FAST_OOF_EN 5 IN2 OOF_EN 2 FAST_OOF_EN 6 IN3 FB_IN OOF_EN 3 FAST...

Page 84: ...hresholds Reg Address Bit Field Type Name Description 0x0046 7 0 R W OOF0_SET_THR Precision OOF Set Threshold The range is up to 500 ppm in 1 16 ppm steps Set Threshold ppm OOFx_SET_THR x 1 16 ppm OOF will be indicated if this is set to 0 0x0047 7 0 R W OOF1_SET_THR 0x0048 7 0 R W OOF2_SET_THR 0x0049 7 0 R W OOF3_SET_THR Table 12 39 Register 0x004A 0x004D Precision OOF Clear Thresholds Reg Address...

Page 85: ...0054 3 0 R W FAST_OOF3_SET_THR Table 12 43 Register 0x0055 0x0058 Fast OOF Clear Thresholds Reg Address Bit Field Type Name Description 0x0055 3 0 R W FAST_OOF0_CLR_THR Fast OOF Clear Threshold The range is from 1 000 ppm to 16 000 ppm in 1000 ppm steps Fast Clear Threshold ppm FAST_OOFx_CLR_THR 1 1000ppm Note that OOF will be indicated if this is set to 0 0x0056 3 0 R W FAST_OOF1_CLR_THR 0x0057 3...

Page 86: ...ro 0x0063 15 8 R W OOF2_RATIO_REF 0x0064 23 16 R W OOF2_RATIO_REF 0x0065 25 24 R W OOF2_RATIO_REF Table 12 48 Register 0x0066 0x069 OOF3 Ratio for Reference Reg Address Bit Field Type Name Description 0x0066 7 0 R W OOF3_RATIO_REF Values calculated by CBPro 0x0067 15 8 R W OOF3_RATIO_REF 0x0068 23 16 R W OOF3_RATIO_REF 0x0069 25 24 R W OOF3_RATIO_REF Table 12 49 Register 0x0092 Fast LOL Enable Reg...

Page 87: ...g Address Bit Field Type Name Description 0x009A 1 R W LOL_SLOW_EN_PLL Enable LOL detection 0 LOL Disabled 1 LOL Enabled Table 12 55 Register 0x009B LOL Detection Window Reg Address Bit Field Type Name Description 0x009B 7 4 R W LOL_SLW_DETWIN_SEL Values calculated by CBPro Table 12 56 Register 0x009D LOL Detection Window Reg Address Bit Field Type Name Description 0x009D 3 2 R W LOL_SLW_VALWIN_SE...

Page 88: ...L Clear 0 Disable Delay for LOL Clear 1 Enable Delay for LOL Clear Extends the time after a clock returns or stabilizes before LOL de asserts Table 12 60 Register 0x00A8 0x00AC LOL Clear Delay Reg Address Bit Field Type Name Description 0x00A9 7 0 R W LOL_CLR_DELAY_DIV256 29 bit value 0x00AA 15 8 0x00AB 23 16 0x00AC 28 24 The LOL Clear Delay value is set by ClockBuilder Pro based on each frequency...

Page 89: ... 1 to initiate NVM copy to registers Table 12 64 Register 0x00E5 Fastlock Extend Enable Reg Address Bit Field Type Name Description 0x00E5 5 R W FASTLOCK_EXTEND_EN Extend Fastlock bandwidth period past LOL Clear 0 Do not extend Fastlock period 1 Extend Fastlock period default Table 12 65 Register 0x00EA 0x00ED Fastlock Extend Length Reg Address Bit Field Type Name Description 0x00EA 7 0 R W FASTLO...

Page 90: ...ded after POR after a Hard Reset by pin or register or after initiating and NVM write The Device Ready register is available on every page in the device at the second to the last serial address 0xFE There is a device ready register at 0x00FE 0x01FE 0x02FE etc Since this is on every page you should not write the page register when reading DEVICE_READY Si5386 Rev E Reference Manual Register Map Skyw...

Page 91: ...fault 1 Enable output 0x0103 2 R W OUT0A_RDIV_FORCE Force R0A output divider divide by 2 0 R0A_REG sets divide value de fault 1 Divide value forced to divide by 2 0x0103 3 R W OUT0A_DIV2_BYP Output divide by 2 bypass 0 Use output divide by 2 default 1 Disable output divide by 2 Setting R0A_REG 0 will not set the divide value to divide by 2 automatically OUT0A_RDIV_FORCE must be set to a value of 1...

Page 92: ...c High 2 3 Reserved 0x0104 7 6 R W OUT0A_CMOS_DRV LVCMOS output impe dance selection See Ta ble 4 8 LVCMOS Out put Impedance and Drive Strength Selections on page 44 for valid selec tions Table 12 70 Register 0x0105 Output OUT0A Differential Amplitude and Common Mode Reg Address Bit Field Type Name Description 0x0105 3 0 R W OUT0A_CM OUT0A Common Mode Voltage selection On ly applies when OUT0A_FOR...

Page 93: ...ndependently configured to use one of the N0 N4 divider outputs as its source Nx_NUM and Nx_DEN for each N divider are set in registers 0x0302 0x0337 for N0 to N4 Five different frequencies can be set in the N dividers N0 N4 and each of the 12 outputs can be configured to use any of the five different frequencies All 12 output drivers are identical in terms of control The single set of description...

Page 94: ...13 OUT2 Signal Format and Configura tion 0x0104 0x0114 OUT2 Differential Amplitude and Common Mode 0x0105 0x0115 OUT2 Source Selection and LVCMOS Inversion 0x0106 0x0116 OUT2 Disable Source 0x0107 0x0117 OUT3 Powerdown Output Enable and R3 Divide by 2 0x0103 0x0118 OUT3 Signal Format and Configura tion 0x0104 0x0119 OUT3 Differential Amplitude and Common Mode 0x0105 0x011A OUT3 Source Selection an...

Page 95: ...0x0103 0x012C OUT7 Signal Format and Configura tion 0x0104 0x012D OUT7 Differential Amplitude and Common Mode 0x0105 0x012E OUT7 Source Selection and LVCMOS Inversion 0x0106 0x012F OUT7 Disable Source 0x0107 0x0130 OUT8 Powerdown Output Enable and R8 Divide by 2 0x0103 0x0131 OUT8 Signal Format and Configura tion 0x0104 0x0132 OUT8 Differential Amplitude and Common Mode 0x0105 0x0133 OUT8 Source S...

Page 96: ...t 1 Force driver always active ZDM OUT6 OUT5 OUT0 OUT0A 0x0140 3 0 R W OUTX_ALWAYS_ON OUT9A OUT9 OUT8 OUT7 Table 12 75 Register 0x0141 Output Disable Mask for LOSXAXB Reg Address Bit Field Type Name Description 0x0141 1 R W OUT_DIS_MSK Mask alarms from disabling all out put drivers 0 Disable All output drivers on alarm default 1 Ignore alarms for output driver disable 0x0141 6 R W OUT_DIS_LOSXAXB_...

Page 97: ... for more information Table 12 77 Register 0x0145 Output Power Down All Reg Address Bit Field Type Name Description 0x0145 0 R W OUT_PDN_ALL Powerdown all output drivers 0 Normal Operation default 1 Powerdown all output drivers Si5386 Rev E Reference Manual Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 97 Rev 1 2 Skyworks Propriet...

Page 98: ...8 0x021B P1 Divider Denominator 32 bit Integer Number 0x020E 0x0211 0x021C 0x0221 P2 Divider Numerator 48 bit Integer Number 0x0208 0x020D 0x0222 0x0225 P2 Divider Denominator 32 bit Integer Number 0x020E 0x0211 0x0226 0x022B P3 Divider Numerator 48 bit Integer Number 0x0208 0x020D 0x022C 0x022F P3 Divider Denominator 32 bit Integer Number 0x020E 0x0211 Table 12 81 Register 0x0230 Px_UPDATE Reg Ad...

Page 99: ...al Division Enable Reg Address Bit Field Type Name Description 0x0233 3 0 R W P2_FRACN_MODE P2 IN2 input divider fractional mode Must be set to 0xB for proper operation 0x0233 4 R W P2_FRAC_EN P2 IN2 in put divider fractional enable 0 Integer only division 1 Fractional or Integer division Table 12 85 Register 0x0234 P3 Factional Division Enable Reg Address Bit Field Type Name Description 0x0234 3 ...

Page 100: ...ges to take effect Table 12 88 Register 0x023F MXAXB Update Reg Address Bit Field Type Name Description 0x023F 1 S MXAXB_UPDATE Set to 1 to update the MXAXB_NUM and MXAXB_DEN values A SOFT_RST may also be used to up date these values Table 12 89 Register 0x0247 0x0249 R0 Divider Reg Address Bit Field Type Name Description 0x0247 7 0 R W R0A_REG 24 bit integer final R0A divider se lection R Divisor...

Page 101: ...r 0x026B 0x0272 User Design Identifier Reg Address Bit Field Type Name Description 0x026B 7 0 R W DESIGN_ID0 ASCII encoded string defined by the ClockBuilder Pro user with user defined space or null pad ding of unused characters A user will normally include a configura tion ID revision ID For example ULT 1A with null character pad ding sets DESIGN_ID0 0x55 DESIGN_ID1 0x4C DESIGN_ID2 0x54 DESIGN_ID...

Page 102: ...Pro 0x028D 4 0 R W OOF3_TRG_THR_EXT Set by CBPro Table 12 94 Registers 0x028E 0x0291 OOFx_CLR_THR_EXT Controls Reg Address Bit Field Type Name Description 0x028E 4 0 R W OOF0_CLR_THR_EXT Set by CBPro 0x028F 4 0 R W OOF1_CLR_THR_EXT Set by CBPro 0x0290 4 0 R W OOF2_CLR_THR_EXT Set by CBPro 0x0291 4 0 R W OOF3_CLR_THR_EXT Set by CBPro Table 12 95 Register 0x0292 OOF stop on LOS Controls Reg Address ...

Page 103: ... Register 0x029D 0x029F Fastlock Delay on LOL Reg Address Bit Field Type Name Description 0x029D 7 0 R W FASTLOCK_DLY_ONLOL Value calculated in CBPro based on pa rameter selected 0x029E 15 8 R W FASTLOCK_DLY_ONLOL 0x029F 19 16 R W FASTLOCK_DLY_ONLOL Table 12 102 Register 0x02A9 0x02AB Fastlock Delay on Input Switch Reg Address Bit Field Type Name Description 0x02A9 7 0 R W FASTLOCK_DLY_ONSW Value ...

Page 104: ...et this bit to 1 to latch the N out put divider registers into operation Setting this self clearing bit to 1 latches the new N output divider register values into operation A Soft Reset will have the same effect Table 12 107 Registers that Follow the N0_NUM and N0_DEN Definitions Register Address Description Size Same as Address 0x030D 0x0312 N1_NUM 44 bit Integer 0x0302 0x0307 0x0313 0x0316 N1_DE...

Page 105: ...elay of the N0 divider ClockBuilder Pro calculates the correct value for this register A Soft Reset of the device SOFT_RST 0x001C 0 1 is required to latch in the new delay value Note that the least significant byte 0x0359 is ignored when the N0 divider is in integer mode Nx_DELAY values are calculated by ClockBuilder Pro tDLY Nx_DELAY 256 x 67 8 ps Table 12 110 Register 0x035B 0x035C N1 Delay Cont...

Page 106: ...ero Delay Mode default 1 Enable Zero Delay Mode 0x0487 2 1 R W ZDM_IN_SEL ZDM Manual Input Source Select when both ZDM_EN 1 and IN_SEL_REGCTRL 0x052A 0 1 0 IN0 default 1 IN1 2 IN2 3 Reserved IN3 already used by ZDM To enable ZDM set ZDM_EN 1 In ZDM the input clock source must be selected manually by using either the ZDM_IN_SEL register bits or the IN_SEL1 and IN_SEL0 device input pins IN_SEL_REGCT...

Page 107: ... Pro it is selectable from 10 Hz to 4 kHz in factors of roughly 2x each ClockBuilder Pro will then determine the values for each of these registers The BW_UPDATE bit 0x0514 0 must be set to cause all of the BWx_PLL FASTLOCK_BWx_PLL and HOLDEXIT_BWx parameters to take effect Table 12 117 Register 0x050E 0x0513 DSPLL Fastlock Loop Bandwidth Reg Address Bit Field Type Name Description 0x050E 7 0 R W ...

Page 108: ...ider is not present in DSPLLs A C or D Table 12 120 Register 0x051C 0x051F M Feedback Divider Denominator 32 bits Reg Address Bit Field Type Name Description 0x051C 7 0 R W M_DEN M feedback divider Denominator 32 bit Integer 0x051D 15 8 0x051E 23 16 0x051F 31 24 Note Note that DSPLL B includes a divide by 5 block in the PLL feedback path before the M divider Register values for the DSPLL B M divid...

Page 109: ... IN_SEL is ignored In both ZDM and non ZDM operation IN_SEL_REGCTRL determines whether register based or pin based manual source selection is used Table 12 124 Register 0x052B Fastlock Control Reg Address Bit Field Type Name Description 0x052B 0 R W FASTLOCK_AUTO_EN Auto Fastlock Enable Disable 0 Disable Auto Fastlock 1 Enable Auto Fastlock default 0x052B 1 R W FASTLOCK_MAN Manually Force Fastlock...

Page 110: ...h in sec onds Window Length 2HOLD_HIST_LEN 1 x 8 3 x 10 7 The holdover logic averages the input frequency over a period of time whose duration is determined by the history average length The average frequency is then used as the holdover frequency See 2 5 Holdover Mode to calculate the window length from the register value Table 12 127 Register 0x052F Holdover History Delay Reg Address Bit Field T...

Page 111: ...DE Selects manual or automatic switching modes Automatic mode can be Revertive or Non revertive 00 Manual default 01 Automatic Non revertive 02 Automatic Revertive 03 Re served 0x0536 2 R W HSW_EN Enable Hitless Switching 0 Disable Hitless switching 1 Enable Hitless switching phase buildout enabled default Table 12 131 Register 0x0537 Input Fault Masks Reg Address Bit Field Type Name Description 0...

Page 112: ... Priority 1 is first and most likely to be selected followed by priorities 2 4 Priority 0 prevents the clock input from being automatically selected though it may still be manually selected When two valid input clocks are assigned the same priority the lowest numbered input will be selected In other words IN0 has priority over IN1 IN3 IN1 has priority over IN2 IN3 etc when the priorities are the s...

Page 113: ...eg Address Bit Field Type Name Description 0x0540 7 0 R W RESERVED Reserved Note 1 This register is used when making certain changes to the device 2 1 1 Updating Registers During Device Operation for more information Table 12 139 Register 0x0588 Fine Hitless Switching PM Length Reg Address Bit Field Type Name Description 0x0588 3 0 R W HSW_FINE_PM_LEN Values set by CBPro Table 12 140 Register 0x05...

Page 114: ...Integrator only on Freeze default 0x059B 6 R W HOLDEXIT_BW_SEL0 Holdover Exit Bandwidth select Only valid when both HOL DEXIT_BW_SEL0 0 and HOLD_RAMP_BYP 1 0 Use Fastlock Bandwidth on Hold over exit 1 Use Holdover Exit Bandwidth on Holdover Exit default 0x059B 7 R W HOLDEXIT_STD_BO 1 Default setting do not modify 0 Reserved Table 12 142 Register 0x059C DSPLL Holdover Exit Control Reg Address Bit F...

Page 115: ...resented to the DSPLL the holdover frequency history measurements will be cleared and will begin to accumulate once again Table 12 144 Register 0x05A4 Hitless Switching Limit Reg Address Bit Field Type Name Description 0x05A4 7 0 R W HSW_LIMIT Value set by CBPro Table 12 145 Register 0x05A5 Hitless Switching Limit Action Reg Address Bit Field Type Name Description 0x05A5 0 R W HSW_LIMIT_ACTION Val...

Page 116: ...iguration Reg Address Bit Field Type Name Description 0x05B1 7 0 R W HOLD_SETTLE_TAR GET Set by CBPro 0x05B2 15 0 R W Si5386 Rev E Reference Manual Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 116 Rev 1 2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 9 2021 116 ...

Page 117: ...ng with the optimum signal thresholds Table 12 152 Register 0x0949 Clock Input Control and Configuration Reg Address Bit Field Type Name Description 0x0949 3 0 R W IN_EN Enable or powerdown the IN3 IN0 input buffers 0 Powerdown input buffer 1 Enable and Power up input buffer 0x0949 7 4 R W IN_PULSED_CMOS_EN Select Pulsed CMOS input buffer for IN3 IN0 See 3 2 Types of Inputs for more information 0 ...

Page 118: ...eld Type Name Description 0x094F 7 4 R W CMOS_HI_THR CMOS Clock input threshold select for in puts IN3 IN0 0 Low threshold Pulsed CMOS 1 Standard Threshold Use with dc cou pled CMOS input clocks Si5386 Rev E Reference Manual Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 118 Rev 1 2 Skyworks Proprietary Information Products and Pro...

Page 119: ...Note that a device Soft Reset 0x001C 0 1 must be issued after changing the settings in this regis ter ClockBuilder Pro handles these bits when changing settings for the device Table 12 159 Register 0x0A05 Output N Divider Power Down Reg Address Bit Field Type Name Description 0x0A05 4 0 R W N_PDNB Powers down the output N4 N0 dividers 0 Powerdown unused N dividers 1 Power up active N dividers See ...

Page 120: ... Divider Auto Disable Reg Address Bit Field Type Name Description 0x0A26 3 R W N3_LOAD_AUTO_DIS Set by CBPro Table 12 164 Register 0x0A2C Output N4 Divider Auto Disable Reg Address Bit Field Type Name Description 0x0A2C 3 R W N4_LOAD_AUTO_DIS Set by CBPro Si5386 Rev E Reference Manual Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com ...

Page 121: ...nce set these register bits will self clear as soon as the entire phase adjust sequence has completed The following tables for N1 dynamic phase adjust work the same as N0 dynamic phase adjust Table 12 168 0x0A3C N1 Dynamic Phase Adjust Step Size Reg Address Bit Field Type Name Description 0x0A3C 7 0 R W N1_PHASE_STEP N1 step size from 1 to 255 in units of Tvco the VCO period Table 12 169 0x0A3D N1...

Page 122: ...ep size from 1 to 255 in units of Tvco the VCO period Table 12 175 0x0A45 N3 Dynamic Phase Adjust Step Size Count Reg Address Bit Field Type Name Description 0x0A45 7 0 R W N3_PHASE_COUNT Lower byte of number of N3 step size changes 0x0A46 15 8 R W N3_PHASE_COUNT Upper byte of number of N3 step size changes Table 12 176 0x0A47 N3 Dynamic Phase Adjust Command Reg Address Bit Field Type Name Descrip...

Page 123: ...namic Phase Adjust Command Reg Address Bit Field Type Name Description 0x0A4B 0 R W N4_PHASE_INC Writing a 1 initiates a phase increment 0x0A4B 1 R W N4_PHASE_DEC Writing a 1 initiates a phase decrement Si5386 Rev E Reference Manual Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 123 Rev 1 2 Skyworks Proprietary Information Products...

Page 124: ...Table 12 182 0x0A4F Static N0 IODELAY Increment and Decrement Reg Address Bit Field Type Name Description 0x0A4F 0 R W N0_IODE LAY_INC_EN Upon power up or hard reset the IODELAY will increment or decre ment depending upon which bit is set 0x0A4F 1 R W N0_IODE LAY_DEC_EN The following tables for N1 static IODELAY adjust work the same as N0 static IODELAY adjust Table 12 183 0x0A50 Static N1 IODELAY...

Page 125: ...ement and Decrement Reg Address Bit Field Type Name Description 0x0A57 0 R W N2_IODE LAY_INC_EN Upon power up or hard reset the IODELAY will increment or decre ment depending upon which bit is set 0x0A57 1 R W N2_IODE LAY_DEC_EN The following tables for N3 static IODELAY control work the same as N0 static IODELAY control Table 12 189 0x0A58 Static N3 IODELAY STEP Reg Address Bit Field Type Name De...

Page 126: ...ay_COUNT Upper Byte of IO DELAY COUNT Table 12 194 0x0A5F N4 IODELAY Static Increment and Decrement Reg Address Bit Field Type Name Description 0x0A5F 0 R W N4_IODE LAY_INC_EN Upon power up or hard reset the IODELAY will increment or decre ment depending upon which bit is set 0x0A5F 1 R W N4_IODE LAY_DEC_EN Table 12 195 Register 0x0B24 Reserved Control Reg Address Bit Field Type Name Description 0...

Page 127: ...ble 12 199 Register 0x0B46 Loss of Signal Clock Disables Reg Address Bit Field Type Name Description 0x0B46 3 0 R W LOS_CLK_DIS Disables LOS clock for IN3 IN0 Must be set to 0 to enable the LOS function of the respective inputs ClockBuilder Pro handles these bits when changing settings for all portions of the device Table 12 200 Register 0x0B47 Disable OOF Internal Clocks Reg Address Bit Field Typ...

Page 128: ...05 0x0B4A 5 R W M_CLK_DIS Disable M divider Must be set to 0 to enable the M divider 0x0B4A 6 R W M_DIV_CAL_DIS Disable M divider calibration Must be set to 0 to allow calibration ClockBuilder Pro handles these bits when changing settings for the device Table 12 204 Register 0x0B57 0x0B58 VCO Calcode Reg Address Bit Field Type Name Description 0x0B57 7 0 R W VCO_RESET_CALCODE Value calculated in C...

Page 129: ...le 12 207 Register 0x0C07 Clock Validation Configuration Reg Address Bit Field Type Name Description 0x0C07 0 R W IN_CLK_VAL_EN Set by CBPro Table 12 208 Register 0x0C08 Clock Validation Configuration Reg Address Bit Field Type Name Description 0x0C08 7 0 R W IN_CLK_VAL_TIME Set by CBPro Si5386 Rev E Reference Manual Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales sky...

Page 130: ...E 0 130 200 1 230 400 2 350 620 3 450 820 4 575 1010 5 700 1200 61 810 13501 71 920 16001 Note 1 In Low Power mode with VDDO 1 8 V OUTx_AMPL may not be set to 6 or 7 2 These amplitudes are based upon 100 Ω differential termination For applications using a custom differential output amplitude the common mode voltage should be selected as shown in the table below These selections along with the sett...

Page 131: ...additional information on the OUTx_FOR MAT_OUTx_AMPL and OUTx_CM controls Si5386 Rev E Reference Manual Appendix Custom Differential Amplitude Controls Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 131 Rev 1 2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 9 2021 131 ...

Page 132: ...ted Section 2 1 1 Updating Registers During Device Operation Removed Recommend Reference Oscillators section and table Revision 0 9 January 2018 Updated 2 1 2 NVM Programming Revision 0 1 September 2017 Initial release Si5386 Rev E Reference Manual Revision History Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 132 Rev 1 2 Skyworks Proprietary ...

Page 133: ...RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Skyworks products are not intended for use in medical lifesaving or life sustaining applications or other equipment in which the failure of the Skyworks products could lead to personal injury death physical or environmental damage Skyworks customers using or selling Skyworks products for use in such applications do so at the...

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