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5.3.3 Output Driver Settings for LVPECL, LVDS, HCSL, and CML

Each differential output has four settings for control:

1. Normal or Low Power Format
2. Amplitude (sometimes called Swing)
3. Common Mode Voltage
4. Stop High or Stop Low

The normal Format setting has a 100 Ω internal resistor between the plus and minus output pins. The Low Power Format setting
removes this 100 Ω internal resistor and then the differential output resistance will be
> 500 Ω. However, as long as the termination impedance matches the differential impedance of the PCB traces, the signal integrity
across the termination impedance will be good. For the same output amplitude, the Low Power Format will use less power than the
Normal Format. The Low Power Format also has a lower rise/fall time than the Normal Format. See the Si5341/40 data sheet for the
rise/fall time specifications. For LVPECL and LVDS standards, ClockBuilder Pro does not support the Low Power Differential Format.
Stop High means that when the output driver is disabled, the plus output will be high, and the minus output will be low. Stop Low means
that when the output driver is disabled, the plus output will be low, and the minus output will be high.

Differential Normal Swing Mode—This is the usual selection for differential outputs and should be used, unless there is a specific
reason to do otherwise. When an output driver is configured in normal swing mode, its output swing is selectable as one of 7 settings
ranging from 200 mVpp_se to 800 mVpp_se in increments of 100 mV. The output impedance in the Normal Swing Mode is 100 Ω
differential.

Differential High Swing Mode—When an output driver is configured in high swing mode, its output swing is configurable as one of 7
settings ranging from 400 mVpp_se to 1600 mVpp_se in increments of 200 mV. The output driver is in high impedance mode and
supports standard 50 Ω PCB traces The use of High Swing mode will result in larger pk-pk output swings that draw less power. The
trade off will be slower rise and fall times.

Vpp_diff is 2 x Vpp_se as shown below:

OUTx

OUTx

Vpp_se

Vpp_se

Vpp_diff = 2*Vpp_se

Vcm

Vcm

Vcm

Figure 5.2. Vpp_se and Vpp_diff

The Format, Amplitude, and Common Mode settings for the various supported standards are shown in the following table.

Table 5.4. Settings for LVDS, LVPECL, and HCSL

OUTx_FORMAT

Standard

VDDO Volts

OUTx_CM (Deci-

mal)

OUTx_AMPL

(Decimal)

001 = Normal Differential

LVPECL

3.3

11

6

001 = Normal Differential

LVPECL

2.5

11

6

002 = Low Power Differential

LVPECL

3.3

11

3

002 = Low Power Differential

LVPECL

2.5

11

3

001 = Normal Differential

LVDS

3.3

3

3

001 = Normal Differential

LVDS

2.5

11

3

001 = Normal Differential

Sub-LVDS

1.8

13

3

002 = Low Power Differential

LVDS

3.3

3

1

002 = Low Power Differential

LVDS

2.5

11

1

002 = Low Power Differential

Sub-LVDS

1.8

13

1

002 = Low Power Differential

3.3

11

3

002 = Low Power Differential

HCSL

2.5

11

3

Si5341, Si5340 Rev D Family Reference Manual • Output Clocks

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com

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Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021

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Summary of Contents for Si5340

Page 1: ...These devices are programmable via a serial interface with in circuit programmable nonvolatile memory NVM ensuring power up with a known frequency configuration RELATED DOCUMENTS Si5341 0 Data Sheet Si5341 0 Device Errata Si5341 0 EVB User Guide Si5341 0 EVB Schematics BOM Layout IBIS models Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 1 Rev ...

Page 2: ...nce Guidelines for Outputs 22 5 3 Output Signal Format 23 5 3 1 Differential Output Terminations 24 5 3 2 Differential Amplitude Controls 24 5 3 3 Output Driver Settings for LVPECL LVDS HCSL and CML 25 5 3 4 LVCMOS Output Terminations 26 5 3 5 LVCMOS Output Impedance and Drive Strength Selection 27 5 3 6 LVCMOS Output Signal Swing 27 5 3 7 LVCMOS Output Polarity 28 5 3 8 Output Enable Disable 29 5...

Page 3: ...i5340 Layout Recommendations 52 11 2 1 Si5340 Applications without a Crystal as the Reference Clock 52 11 2 2 Si5340 Crystal Guidelines 53 12 Power Management 56 12 1 Power Management Features 56 12 2 Power Supply Recommendations 56 12 3 Grounding Vias 56 12 4 Power Supply Sequencing 57 13 Base vs Factory Preprogrammed Devices 58 13 1 Base Devices Also Known as Blank Devices 58 13 2 Factory Prepro...

Page 4: ...rs Si5340 106 14 3 6 Page A Registers Si5340 107 14 3 7 Page B Registers Si5340 108 15 Appendix Setting the Differential Output Driver to Non Standard Amplitudes 109 16 Revision History 110 Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 4 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Not...

Page 5: ...document Real time changes to the frequency plan and other operating settings are supported by the devices However describing all the possible changes are not a primary purpose of this document Refer to Applications Notes and Knowledge Base article links within the ClockBuilder Pro GUI for information on how to implement the most common real time frequency plan changes The primary purpose of the s...

Page 6: ...L 1 0 IN1 IN2 XB XA XTAL OSC Multi Synth OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 Multi Synth Multi Synth Multi Synth Multi Synth Si5340 Si5341 PLL NVM I2C SPI Control Status Figure 1 1 Block Diagram Si5341 40 Si5341 Si5340 Rev D Family Reference Manual Overview Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 6 Rev 1 3 Skyworks Propriet...

Page 7: ...n of selections The final configuration settings can be saved written to a device or written to the EVB and a custom part number can be created ClockBuilder Pro integrates all the datasheets application notes and information that might be helpful in one environment It is intended that customers will use the software tool for the proper configuration of the device Register map descriptions are give...

Page 8: ...teger dividers R provide further frequency division if required The frequency configuration of the device is programmed by setting the input dividers P the DSPLL feedback fractional divider M_NUM M_DEN the MultiSynth fractional dividers N_NUM N_DEN and the output integer dividers R Silicon Labs Clockbuilder Pro configuration utility determines the optimum divider values for any desired input and o...

Page 9: ...t must be written to cause a newly written divider value to take effect 4 Output N dividers Ultra low jitter in fractional and integer modes MultiSynth divider Integer or fractional divide values 44 bit numerator 32 bit denominator Min value is 10 Maximum value is 212 1 Each N divider has an update bit that must be written to cause a newly written divider value to take effect In addition there is ...

Page 10: ...B 25MHz 48 54MHz XTAL OSC P2 P1 P0 IN0 IN0 IN1 IN1 IN2 IN2 FDEC FINC Frequency Control N0n N0d t0 N2n N2d N3n N3d N4n N4d t2 t3 t4 N1n N1d t1 MultiSynth SYNC Dividers Drivers Status Monitors LOL INTR Pxaxb Figure 2 1 Si5341 Detailed Block Diagram Si5341 Si5340 Rev D Family Reference Manual Functional Description Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www s...

Page 11: ...R2 R3 R1 OUT0 VDDO0 OUT0 OUT2 VDDO2 OUT2 OUT3 VDDO3 OUT3 OUT1 VDDO1 OUT1 Dividers Drivers 25MHz 48 54MHz XTAL OSC Pxaxb VDD VDDA 3 Figure 2 2 Si5340 Detailed Block Diagram Si5341 Si5340 Rev D Family Reference Manual Functional Description Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 11 Rev 1 3 Skyworks Proprietary Information Products and Pro...

Page 12: ...ice All regis ters will be restored to their default values SOFT_RST 001C 0 001C 0 Performs a soft reset Resets the device while it does not re download the register configuration from NVM The Si541 40 is fully configurable using the serial interface I2C or SPI At power up the device downloads its default register values from internal non volatile memory NVM Application specific default configurat...

Page 13: ...s the internal NVM burn sequence writing NVM from the internal registers Do not access ANY other registers than DEVICE_READY during the NVM burn process Doing so may corrupt the NVM burn in progress 4 Poll DEVICE_READY until DEVICE_READY 0x0F waiting for completion of NVM burn sequence 5 Set NVM_READ_BANK 0x00E4 0 1 This will download the NVM contents back into non volatile memory registers 6 Poll...

Page 14: ...s they are read from NVM Note that this includes accesses to the PAGE register Si5341 Si5340 Rev D Family Reference Manual Powerup and Initialization Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 14 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice July 26 2021 14 ...

Page 15: ... crystals with CL specifications as high as 18 pF can also be used When using crystals with CL specs higher than 8 pf it is not generally recommended to use external capacitors from XA XB to ground to increase the crystal load capacitance Rather the frequency offset due to CL mismatch can be adjusted using the XAXB_FREQ_OFFSET word which allows frequency adjustments of up to 1000 ppm See 11 Crysta...

Page 16: ...he TCXO as close to the Si5340 41 as possible to minimize PCB trace length In addition ensure that both the Si5340 41 and the TCXO are both connected directly to the ground plane The above figure includes the recommended method of connecting a clipped sine wave TCXO to the Si5340 41 Because the Si5340 41 provides DC bias at the XA and XB pins the 800 mV peak peak swing can be input directly into t...

Page 17: ...ion line if used C1 INxb This cap should have less than 20 ohms of capacitive reactance at the clock input frequency Only when 3 3V LVCMOS driver is present use R2 845 ohm and R1 267 ohm if needed to keep the signal at INx 3 6 Vpp_se Including C1 6 pf may improve the output jitter due to faster input slew rate at INx If attenuation is not needed for Inx 3 6Vppse make R1 0 ohm and omit C1 R2 and th...

Page 18: ...en the XTAL or external reference clock on the XA XB pins Default is 0 XTAL Set to 1 to use an external refer ence oscillator IN_SEL_REGCTRL 0021 0 Determines pin or register clock input selection IN_SEL 0021 2 1 Selects the input when in register input selection mode IN_EN 0949 3 0 Allows enabling disabling IN0 IN1 IN2 and FB_IN when not in use Table 4 3 XAXB Pre Scale Divide Ratio Register Setti...

Page 19: ...P1 FB_IN FB_IN IN2 IN2 P2 LOL Si5341 40 XB XA OSC Pfb Md LOSXAXB LOS1 LOS2 LOSFB LOL LOS0 LOS1 LOS2 LOSXAB INTR Pxaxb Figure 4 3 LOS and LOL Fault Monitors Si5341 Si5340 Rev D Family Reference Manual Clock Inputs Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 19 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subje...

Page 20: ...ot have an LOS detector LOSREF 0x000C 2 Loss of Signal for the input that has been selected LOL 0x000C 3 Loss of Lock for the PLL SMBUS_TIMEOUT 0x000C 5 The SMB bus has a timeout LOSIN 3 0 0x000D 3 0 Loss of Signal for the FB_IN IN2 IN1 IN0 inputs Sticky Status Register Bits SYSINCAL_FLG 0x0011 0 Sticky bit for SYSINCAL LOSXAXB_FLG 0x0011 1 Sticky bit for LOSXAXB LOSREF_FLG 0x0011 2 Sticky bit for...

Page 21: ... the INTR pin LOSREF_INTR_MSK 0x0017 2 1 LOSREF_FLG is prevented from asserting the INTR pin LOL_INTR_MSK 0x0017 3 1 LOL_FLG is prevented from asserting the INTR pin SMB_TMOUT_INTR_MSK 0x0017 5 1 SMBUS_TIMEOUT_FLG is prevented from asserting the INTR pin LOSIN _INTR_MSK 3 0 0x0018 3 0 1 LOS_FLG is prevented from asserting the INTR pin mask mask mask mask mask mask LOL_FLG LOSXAXB_FLG LOSIN_FLG 3 L...

Page 22: ...quencies at least 20 MHz apart 2 Adjacent frequency values that are integer multiples of one another are okay and these outputs should be grouped accordingly Noting that because 155 52 x 4 622 08 and 156 25 x 4 625 it is acceptable to place 155 52 MHz close to 622 08 MHz and 156 25 MHz close to 625 MHz 3 Unused outputs can be used to separate clock outputs that might otherwise interfere with one a...

Page 23: ... CMOS output can create much more crosstalk than differential outputs so extra care must be taken in their pin replacement so that other clocks that need the lowest jitter are not on nearby pins See AN862 Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems for additional information Table 5 2 Output Signal Format Control Registers Setting Name Hex Address Bit Fi...

Page 24: ... amplitude of each output can be controlled with the following registers See XREF Appendix A for register settings for non standard amplitudes Table 5 3 Differential Output Voltage Swing Amplitude Control Registers Setting Name Hex Address Bit Field Function Si5341 Si5340 OUT0_AMPL OUT1_AMPL OUT2_AMPL OUT3_AMPL OUT4_AMPL OUT5_AMPL OUT6_AMPL OUT7_AMPL OUT8_AMPL OUT9_AMPL 010A 6 4 010F 6 4 0114 6 4 ...

Page 25: ... to 800 mVpp_se in increments of 100 mV The output impedance in the Normal Swing Mode is 100 Ω differential Differential High Swing Mode When an output driver is configured in high swing mode its output swing is configurable as one of 7 settings ranging from 400 mVpp_se to 1600 mVpp_se in increments of 200 mV The output driver is in high impedance mode and supports standard 50 Ω PCB traces The use...

Page 26: ... for more information The output differential driver can produce a wide range of output amplitudes that includes CML amplitudes See XREF Appendix A for additional information 5 3 4 LVCMOS Output Terminations LVCMOS outputs are dc coupled as shown in the figure below 3 3 V 2 5 V 1 8 V LVCMOS VDDO 3 3 V 2 5 V 1 8 V 50 Rs 50 Rs DC Coupled LVCMOS OUTx OUTx Si5341 40 Figure 5 3 LVCMOS Output Terminatio...

Page 27: ...recommended Table 5 5 LVCMOS Drive Strength Control Registers Setting Name Hex Address Bit Field Function Si5341 Si5340 OUT0_CMOS_DRV OUT1_CMOS_DRV OUT2_CMOS_DRV OUT3_CMOS_DRV OUT4_CMOS_DRV OUT5_CMOS_DRV OUT6_CMOS_DRV OUT7_CMOS_DRV OUT8_CMOS_DRV OUT9_CMOS_DRV 0109 7 6 010E 7 6 0113 7 6 0118 7 6 011D 7 6 0122 7 6 0127 7 6 012C 7 6 0131 7 6 013B 7 6 0113 7 6 0118 7 6 0127 7 6 012C 7 6 LVCMOS output ...

Page 28: ...NV OUT3_INV OUT4_INV OUT5_INV OUT6_INV OUT7_INV OUT8_INV OUT9_INV 010B 7 6 0110 7 6 0115 7 6 011A 7 6 011F 7 6 0124 7 6 0129 7 6 012E 7 6 0133 7 6 0138 7 6 0115 7 6 011A 7 6 0129 7 6 012E 7 6 Controls output polarity of the OUTx and OUTxb pins when in LVCMOS mode Selections are as follows OUTx_INV OUTx OUTxb Comment 0 0 CLK CLK Both in phase default 0 1 CLK CLKb OUTxb inverted 1 0 CLKb CLKb OUTx a...

Page 29: ...LE_LOW 0102 0 0 Disables all outputs 1 All outputs are not disabled by this signal but may be disabled by other signals or the OEB pin See figure above OUT0_OE OUT1_OE OUT2_OE OUT3_OE OUT4_OE OUT5_OE OUT6_OE OUT7_OE OUT8_OE OUT9_OE 0108 1 010D 1 0112 1 0117 1 011C 1 0121 1 0126 1 012B 1 0130 1 013A 1 0112 1 0117 1 0126 1 012B 1 0 Specific output disabled 1 Specific output is not disabled The OEB p...

Page 30: ...ver when disabled Selecta ble as Disable logic low Disable logic high 5 3 10 Synchronous Asynchronous Output Disable Feature Outputs can be configured to disable synchronously or asynchronously In synchronous disable mode the output will wait until a clock period has completed before the driver is disabled This prevents unwanted runt pulses from occurring when disabling an output In asynchronous d...

Page 31: ...T3_MUX_SEL OUT4_MUX_SEL OUT5_MUX_SEL OUT6_MUX_SEL OUT7_MUX_SEL OUT8_MUX_SEL OUT9_MUX_SEL 010B 2 0 0110 2 0 0115 2 0 011A 2 0 011F 2 0 0124 2 0 0129 2 0 012E 2 0 0133 2 0 013D 2 0 0115 2 0 011A 2 0 0129 2 0 012E 2 0 Connects the output drivers to one of the N dividers Selections are N0 N1 N2 N3 and N4 for each output divider Si5341 Si5340 Rev D Family Reference Manual Output Clocks Skyworks Solutio...

Page 32: ... path Zero Delay Mode performance will degrade with low values of phase detector frequency Fpfd For this reason ClockBuilder Pro will not enable Zero Delay Mode with an Fpfd of less than 128 kHz When the DSPLL is set for Zero Delay Mode ZDM a hard reset request from either the RSTb pin or RST_REG register bit will have a delay of 750 ms before executing Any subsequent register writes to the device...

Page 33: ...mal mode All other values must not be written Si5341 Si5340 Rev D Family Reference Manual Output Clocks Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 33 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice July 26 2021 33 ...

Page 34: ... may be necessary to adjust the Nx_NUM value while keeping the ratio of Nx_NUM Nx_DEN the same When the FINC or FDEC pin or register bit is asserted the selected N dividers will have their numerator changed by the addition or subtraction of the Nx_FSTEPW so that an FINC will increase the output frequency and an FDEC will decrease the output frequency An FINC or FDEC can be followed by another FINC...

Page 35: ... after Revision B Either the new or old values below may be written to Revision D or later devices without issue No system software changes are necessary for legacy systems When writing old values note that reading back these registers will not give the written old values but will reflect the new values Silicon Labs recommends using the new values for all Revision D and later designs since the wri...

Page 36: ... task 1 Use the Frequency Increment Decrement Pins or register bits 2 Write directly to the numerator or denominator of the Nx divider The details of both methods are covered in 6 1 Using the N Dividers for DCO Applications 7 4 Dynamic Changes to Output Frequencies while Changing PLL Settings Using a CBPro Register Map This section applies to the following scenario 1 A CBPro generated register map...

Page 37: ...able lists register settings of interest for the I2C SPI Table 8 1 I2C SPI Register Settings Register Name Hex Address Bit Field Function Si5341 Si5340 IO_VDD_SEL 0x0943 0 0x0943 0 The IO_VDD_SEL configuration bit optimizes the VIL VIH VOL and VOH thresholds to match the VDDS voltage By default the IO_VDD_SEL bit is set to the VDD option The serial interface pins are always 3 3 V tolerant even whe...

Page 38: ...L VDD VDDI2C To I2 C Bus or Host A0 A1 LSBs of I2 C Address I2 C Figure 8 2 I2C Configuration The 7 bit slave device address of the Si5341 40 consists of a 5 bit fixed address plus two pins that are selectable for the last two bits as shown in the following figure Slave Address 1 1 1 0 1 A0 0 1 2 3 4 5 6 A1 Figure 8 3 7 bit I2C Slave Address Bit Configuration Data is transferred MSB first in 8 bit...

Page 39: ...ion is also supported as shown in the following figure 1 Read 0 Write A Acknowledge SDA LOW N Not Acknowledge SDA HIGH S START condition P STOP condition Read Operation Single Byte S 0 A Reg Addr 7 0 Slv Addr 6 0 A P Read Operation Burst Auto Address Increment Reg Addr 1 S 1 A Slv Addr 6 0 Data 7 0 P N S 0 A Reg Addr 7 0 Slv Addr 6 0 A P S 1 A Slv Addr 6 0 Data 7 0 A P N Data 7 0 Host Si5341 40 Ho...

Page 40: ...urst Write Command is terminated by de asserting CSb CSb high 3 There is no limit to the number of data bytes that may follow the Burst Write command but the address will wrap around to 0 in the byte after address 255 is written Writing or reading data consist of sending a Set Address command followed by a Write Data or Read Data command The Write Data Address Increment or Read Data Address Increm...

Page 41: ...t read only read increment Set Address and Read Data Address Increment Set Address and Read Data Set Addr Addr 7 0 Read Data Data 7 0 Set Addr Addr 7 0 Read Data Data 7 0 Set Addr Addr 7 0 Read Data Data 7 0 Read Data Addr Inc Data 7 0 Read Data Addr Inc Data 7 0 Set Addr Addr 7 0 Read Data Addr Inc Data 7 0 Si5341 40 Host Si5341 40 Host Figure 8 8 Example of Reading Three Data Bytes Using the Rea...

Page 42: ...rite Data or Write Data Address Increment Command 2 SCLK Periods Previous Command Next Command 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 6 7 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 6 7 Si5341 40 Host Si5341 40 Host Don t Care High Impedance 2 0 SCLK Periods Figure 8 10 SPI Write Data and Write Data Address Increment Instruction Timing Si5341 Si5340 Rev D Family Reference Manual Serial Interface Skyworks Sol...

Page 43: ...2 3 4 5 6 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 Si5341 40 Host Si5341 40 Host Don t Care High Impedance 1st data byte base address 6 Next Command 6 7 7 7 7 7 7 7 2 0 SCLK Periods 2 0 SCLK Periods Note that for all SPI communication the chip select CS must be high for the minimum time period between commands When chip select goes high it indicates the termination of the command The SCLK can b...

Page 44: ...programming of Si5341 40 sample devices Refer to the https www silabs com products development tools timing cbprogrammer product web page for information about this kit Si5341 Si5340 Rev D Family Reference Manual Field Programming Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 44 Rev 1 3 Skyworks Proprietary Information Products and Product Inf...

Page 45: ...nual for more information Si5341 Si5340 Rev D Family Reference Manual Recommended Crystals and External Oscillators Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 45 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice July 26 2021 45 ...

Page 46: ...tions Top Layer Layer 1 on page 47 is the top layer layout of the Si5341 device mounted on the top PCB layer This particular layout was designed to implement either a crystal or an external oscillator as the XAXB reference The crystal oscillator area is outlined with the white box around it In this case the top layer is flooded with ground Note that this layout has a resistor in series with each p...

Page 47: ...oute GND power planes traces or locate components on the other side below the crystal shield If necessary a ground layer may be placed under the crystal shield plane as long as it is at least 0 05 below the crystal shield layer Figure 11 1 64 pin Si5341 Crystal Layout Recommendations Top Layer Layer 1 Note the vias that are shown for the center ground pad so that there is a low impedance path to g...

Page 48: ...ane and shows the clock output power supply traces The void underneath the crystal shield is continued Si5341 Si5340 Rev D Family Reference Manual Crystal and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 48 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Wit...

Page 49: ...Layer 5 The following figure is another ground plane similar to Layer 3 Si5341 Si5340 Rev D Family Reference Manual Crystal and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 49 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice July 26 2021 49 ...

Page 50: ...rystal and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 50 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice July 26 2021 50 ...

Page 51: ...line of vias through the ground flood on either side of the output clocks to ensure that the ground flood immediately next to the differential pairs has a low inductance path to the ground plane on Layers 3 and 6 Figure 11 8 Bottom Layer Ground Flooded Layer 8 Si5341 Si5340 Rev D Family Reference Manual Crystal and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax...

Page 52: ...s from noise and other signals 11 2 1 Si5340 Applications without a Crystal as the Reference Clock If the application does not use a crystal then the X1 and X2 pins should be left as no connect and should not be tied to ground In addition there is no need for a crystal shield or the voids underneath the shield If there is a differential external clock input on XAXB there should be a termination ci...

Page 53: ...ane Figure 11 10 Crystal Shield Layer 2 The following figure is the ground plane and shows a void underneath the crystal shield Figure 11 11 Ground Plane Layer 3 The following figure is a power plane showing the clock output power supply traces The void underneath the crystal shield is continued Si5341 Si5340 Rev D Family Reference Manual Crystal and Device Circuit Layout Recommendations Skyworks ...

Page 54: ...e shield Layer 6 and layer 1 are mainly used for low speed CMOS control and status signals for which crosstalk is not a significant issue PCB ground can be placed under the X1X2 shield as long as the PCB ground is at least 0 05 inches below it Si5341 Si5340 Rev D Family Reference Manual Crystal and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sal...

Page 55: ... preferred because of its increased immunity to common mode noise All clock I O runs should be properly terminated Si5341 Si5340 Rev D Family Reference Manual Crystal and Device Circuit Layout Recommendations Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 55 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject t...

Page 56: ...ach VDD for optimal performance Because of the extensive internal voltage regulation this will be sufficient unless the power supply has very high noise If the power supply might have very high noise then it is suggested to include an optional single 0603 resistor ferrite bead in series with each supply to enable additional filtering This resistor ferrite should initially be a 0 Ω resistor If addi...

Page 57: ...ad the register with the contents of the NVM and any unsaved changes will be lost One may observe that when powering up the VDD 1 8 V rail first that the VDDA 3 3 V rail will initially follow the 1 8 V rail Likewise if the VDDA rail is powered down first then it will not drop far below VDD until VDD itself is powered down This is due to the pad I O circuits which have large MOSFET switches to sele...

Page 58: ...n that includes specifying the XAXB reference frequency type the clock input frequencies the clock output frequencies as well as the other options such as automatic clock selection loop BW etc The ClockBuilder software is required to select among all of these options and to produce a project file which Silicon Labs uses to preprogram all devices with custom orderable part number custom OPN Custom ...

Page 59: ...se preprogrammed devices are inherently quite different from one another the default power up values of the registers can be determined using the custom OPN utility Table 14 1 Register Map Paging Descriptions Page Start Address Hex Start Address Decimal Contents Page 0 0000h 0 Alarms interrupts reset device ID revision ID Page 1 0100h 256 Clock output configuration Page 2 0200h 512 P R dividers sc...

Page 60: ... Four digit base part number one nibble per digit Example Si5341A A GM The base part number OPN is 5341 which is stored in this register 0x0003 15 8 R PN_BASE Table 14 5 0x0004 Device Speed Synthesis Mode Grade Reg Address Bit Field Type Setting Name Description 0x0004 7 0 R GRADE One ASCII character indicating the device speed grade 0 A 1 B 2 C 3 D Table 14 6 0x0005 Device Revision Reg Address Bi...

Page 61: ... Pro Table 14 9 0x000B I2C Address Reg Address Bit Field Type Setting Name Description 0x000B 6 2 R W I2C_ADDR The upper 5 bits of the 7 bit I2C address The lower 2 bits are controlled by the A1 and A0 pins Table 14 10 0x000C Status Bits Reg Address Bit Field Type Setting Name Description 0x000C 0 R SYSINCAL 1 if the device is calibrating 0x000C 1 R LOSXAXB 1 if there is no signal at the XA pin as...

Page 62: ...ield Type Setting Name Description 0x0017 0 R W SYSINCAL_INTR_MSK 1 to mask SYSINCAL_FLG from causing an interrupt 0x0017 1 R W LOSXAXB_INTR_MSK 1 to mask the LOSXAXB_FLG from causing an interrupt 0x0017 2 R W LOSREF_INTR_MSK 1 to mask LOSREF_FLG from causing an interrupt 0x0017 3 R W LOL_INTR_MSK 1 to mask LOL_FLG from causing an interrupt 0x0017 5 R W SMB_TMOUT_INTR_MSK 1 to mask SMBUS_TIMEOUT_F...

Page 63: ...ow power mode 0x001E 1 R W HARD_RST 1 causes hard reset The same as power up except that the serial port access is not held at reset NVM is re downloaded This does not self clear so after setting the bit it must be cleared 0 No reset 0x001E 2 S SYNC 1 to reset all output R dividers to the same state Table 14 19 0x0021 Input Clock Selection Reg Address Bit Field Type Setting Name Description 0x0021...

Page 64: ..._VAL_TIME Clock Input 3 same as above When an input clock is gone and therefore has an active LOS alarm if the clock returns there is a period of time that the clock must be within the acceptable range before the alarm is removed This is the LOS_VAL_TIME Table 14 23 0x002E 0x002F LOS0 Trigger Threshold Reg Address Bit Field Type Setting Name Description 0x002E 7 0 R W LOS0_TRG_THR 16 bit Threshold...

Page 65: ...ticular frequency plan Table 14 28 0x0038 0x0039 LOS1 Clear Threshold Reg Address Bit Field Type Setting Name Description 0x0038 7 0 R W LOS1_CLR_THR 16 bit Threshold Value 0x0039 15 8 R W LOS1_CLR_THR ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 1 given a particular frequency plan Table 14 29 0x003A 0x003B LOS2 Clear Threshold Reg Address Bit Field Type Set...

Page 66: ...wing are the pre divider values for the above listed registers values Register Value Decimal Divider Value 0 1 bypass 1 2 2 4 3 8 4 16 5 32 6 64 7 128 8 256 9 512 10 1024 11 2048 12 4096 13 8192 14 16384 15 32768 16 65536 Table 14 32 0x009E Reg Address Bit Field Type Setting Name Description 0x009E 7 4 R W LOL_SET_THR Configures the loss of lock set thresholds Si5341 Si5340 Rev D Family Reference ...

Page 67: ...le memory Table 14 36 0x00F6 Reg Address Bit Field Type Setting Name Description 0x00F6 0 R REG_0XF7_INTR Set by CBPro 0x00F6 1 R REG_0XF8_INTR Set by CBPro 0x00F6 2 R REG_0XF9_INTR Set by CBPro Table 14 37 0x00F7 Reg Address Bit Field Type Setting Name Description 0x00F7 0 R SYSINCAL_INTR Set by CBPro 0x00F7 1 R LOSXAXB_INTR Set by CBPro 0x00F7 2 R LOSREF_INTR Set by CBPro 0x00F7 3 R LOL_INTR Set...

Page 68: ...egisters This register is repeated on every page therefore a page write is not ever required to read the DEVICE_READY Si5341 Si5340 Rev D Family Reference Manual Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 68 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice July 26 20...

Page 69: ...t the R0_REG value will be ignored while OUT0_RDIV_FORCE2 1 See R0_REG registers 0x024A 0x024C for more information Table 14 42 0x0109 Clock Output 0 Format Reg Address Bit Field Type Setting Name Description 0x0109 2 0 R W OUT0_FORMAT 0 Reserved 1 normal differential 2 low power differential 3 reserved 4 LVCMOS 5 7 Reserved 0x0109 3 R W OUT0_SYNC_EN 0 disable 1 Enable Enable disable synchronized ...

Page 70: ...me Description 0x010B 2 0 R W OUT0_MUX_SEL Output driver 0 input mux select This selects the multi synth N divider that is connected to the output driver 0 N0 1 N1 2 N2 3 N3 4 N4 5 7 Reserved 0x010B 3 R W OUT0_VDD_SEL_EN Output Driver VDD Select Enable Set to 1 for normal operation 0x010B 5 4 R W OUT0_VDD_SEL Output Driver VDD Select 0 3 3V 1 1 8V 2 2 5V 3 Reserved 0x010B 7 6 R W OUT0_INV 0 CLK an...

Page 71: ...2 OUT5_FORMAT _SYNC_EN DIS_STATE _CMOS_DRV 0x0109 0x0123 OUT5_CM OUT5_AMPL 0x010A 0x0124 OUT5_MUX_SEL OUT5_VDD_SEL_EN OUT5_VDD_SEL OUT5_INV 0x010B 0x0126 OUT6_PDN OUT6_OE OUT6_RDIV_FORCE2 0x0108 0x0127 OUT6_FORMAT _SYNC_EN DIS_STATE _CMOS_DRV 0x0109 0x0128 OUT6_CM OUT6_AMPL 0x010A 0x0129 OUT6_MUX_SEL OUT6_VDD_SEL_EN OUT6_VDD_SEL OUT6_INV 0x010B 0x012B OUT7_PDN OUT7_OE OUT7_RDIV_FORCE2 0x0108 0x012...

Page 72: ...ing Name Description 0x0141 5 R W OUT_DIS_LOL_MS K Set by CBPro 0x0141 7 R W OUT_DIS_MSK_LO S_PFD Set by CBPro Table 14 48 0x0145 Power Down All Outputs Reg Address Bit Field Type Setting Name Description 0x0145 0 R W OUT_PDN_ALL 0 no effect 1 all drivers powered down Si5341 Si5340 Rev D Family Reference Manual Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksi...

Page 73: ...4 3 divider value 8 The following registers configure the P dividers which are located at the four input clocks seen in Figure 2 1 Si5341 Detailed Block Diagram on page 10 ClockBuilder Pro calculates the correct values for the P dividers Table 14 51 0x0208 0x020D P0 Dividers Reg Address Bit Field Type Setting Name Description 0x0208 7 0 R W P0 48 bit Integer Number 0x0209 15 8 R W P0 0x020A 23 16 ...

Page 74: ...ddress Bit Field Type Setting Name Description 0x021C 7 0 R W P2 48 bit Integer Number 0x021D 15 8 R W P2 0x021E 23 16 R W P2 0x021F 31 24 R W P2 0x0220 39 32 R W P2 0x0221 47 40 R W P2 Table 14 56 0x0222 0x0225 P2 Divider Enable Set Reg Address Bit Field Type Setting Name Description 0x0222 7 0 R W P2_SET Set by CBPro 0x0223 15 8 R W P2_SET 0x0224 23 16 R W P2_SET 0x0225 31 24 R W P2_SET Si5341 S...

Page 75: ... bit to cause a change to the P1 divider to take effect 0x0230 2 S P2_UPDATE Must write a 1 to this bit to cause a change to the P2 divider to take effect 0x0230 3 S P3_UPDATE Must write a 1 to this bit to cause a change to the P3 divider to take effect Bits 7 4 of this register have no function and can be written to any value Table 14 60 0x0235 0x023A M Divider Numerator Reg Address Bit Field Typ...

Page 76: ...e all other values follow the formula in the bit description above divide by 2 requires an extra bit to be set For divide by 2 set OUT0_RDIV_FORCE2 1 See the description for register bit 0x0108 2 in this register map The R1 R9 dividers follow the same format as the R0 divider description above Table 14 64 R Dividers for Outputs 1 2 3 4 5 6 7 8 9 Register Address Setting Name Size Same as Address 0...

Page 77: ...A12345 GM 12345 is the OPN unique identifier which sets OPN_ID0 0x31 OPN_ID1 0x32 OPN_ID2 0x33 OPN_ID3 0x34 OPN_ID4 0x35 0x0279 15 8 R W OPN_ID1 0x027A 23 16 R W OPN_ID2 0x027B 31 24 R W OPN_ID3 0x027C 39 32 R W OPN_ID4 Part numbers are of the form Si Part Num Base Grade Device Revision OPN ID Temp Grade Package ID Examples Si5341C A12345 GM Applies to a custom OPN Ordering Part Number device Thes...

Page 78: ... Bit Field Type Setting Name Description 0x027E 7 0 R W BaseLine ID An identifier for the device NVM without the frequency plan programmed into NVM Si5341 Si5340 Rev D Family Reference Manual Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 78 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Ch...

Page 79: ... Description 0x030C 0 S N0_UPDATE Must write a 1 to this bit to cause N0 divider changes to take effect Table 14 72 N1 N2 N3 Numerator and Denominators Register Address Setting Name Size Same as Address 0x030D 0x0312 N1_NUM 44 bit Integer Number 0x0302 0x0307 0x0313 0x0316 N1_DEN 32 bit Integer Number 0x0308 0x030B 0x0318 0x031D N2_NUM 44 bit Integer Number 0x0302 0x0307 0x031E 0x0321 N2_DEN 32 bi...

Page 80: ... a 1 to this bit will update all N dividers to the latest value written to them A specific N divider that has not been changed will not be affected by writing a 1 to this bit When this bit is written to a 1 all other bits in this byte should only be written to a 0 Table 14 78 0x0339 FINC FDEC Masks Reg Address Bit Field Type Setting Name Description 0x0339 4 0 R W N_FSTEP_MSK 0 to enable FINC FDEC...

Page 81: ...ue The Nx_NUM register value does not change when an FINC or FDEC is performed so that the starting point of Nx_NUM is in the Nx_NUM register Table 14 80 Frequency Step Word for N1 N2 N3 N4 Register Address Setting Name Size Same as Address 0x0341 0x0346 N1_FSTEPW 44 bit Integer Number 0x033B 0x0340 0x0347 0x034C N2_FSTEPW 44 bit Integer Number 0x033B 0x0340 0x034D 0x0352 N3_FSTEPW 44 bit Integer ...

Page 82: ...the Si5341 40 IO_VDD_SEL 1 8 V the host should write the IO_VDD_SEL configuration bit to the VDDA option This will ensure that both the host and the serial interface are operating at the optimum voltage thresholds The IO_VDD_SEL bit also affects the status pin levels and control pin thresholds When IO_VDD_SEL 0 the status outputs will have a VOH of 1 8 V When IO_VDD_SEL 1 the status outputs will h...

Page 83: ...al used as a DCO Slightly lower output jitter may occur when the Phase Interpolator is bypassed 1 Bits in this field correspond to the N dividers as N4 N3 N2 N1 N0 A soft reset reg 0x001C 0 should be asserted after changing any of these bits If it is expected that any of the N dividers will be changing from integer to fractional it is recommended that the corresponding bits be initialized to 0 so ...

Page 84: ...CAL CODE 12 bit value 0x0B58 11 8 R W VCO_RESET_CAL CODE 14 3 Si5340 Registers Because preprogrammed devices are inherently quite different from one another the default power up values of the registers can be determined using the Custom OPN Utility Some registers that are listed in the Data Sheet Addendum are not documented in the Register Map below because they are set and maintained by Clock Bui...

Page 85: ...N_BASE Four digit base part number one nibble per digit Example Si5340A A GM The base part number OPN is 5340 which is stored in this register 0x0003 15 8 R PN_BASE Table 14 96 0x0004 Device Speed Synthesis Mode Grade Reg Address Bit Field Type Setting Name Description 0x0004 7 0 R GRADE One ASCII character indicating the device speed grade 0 A 1 B 2 C 3 D Table 14 97 0x0005 Device Revision Reg Ad...

Page 86: ...ckBuilder Pro Table 14 100 0x000B I2C Address Reg Address Bit Field Type Setting Name Description 0x000B 6 0 R W I2C_ADDR 7 bit I2C Address Table 14 101 0x000C Status Bits Reg Address Bit Field Type Setting Name Description 0x000C 0 R SYSINCAL 1 if the device is calibrating 0x000C 1 R LOSXAXB 1 if there is no signal at the XA pin as the LOS detector is only connected to the XA pin 0x000C 2 R LOSRE...

Page 87: ...L_INTR_MSK 1 to mask SYSINCAL_FLG from causing an interrupt 0x0017 1 R W LOSXAXB_INTR_MSK 1 to mask the LOSXAXB_FLG from caus ing an interrupt 0x0017 2 R W LOSREF_INTR_MSK 1 to mask the LOSREF_FLG from causing an interrupt 0x0017 3 R W LOL_INTR_MSK 1 to mask the LOL_FLG from causing an interrupt 0x0017 5 R W SMB_TMOUT_INTR_MSK 1 to mask SMBUS_TIMEOUT_FLG from causing an interrupt These are the int...

Page 88: ...etting Name Description 0x001E 0 R W PDN 1 to put the device into low power mode 0x001E 1 R W HARD_RST 1 causes hard reset The same as power up except that the serial port access is not held at reset NVM is re downloaded This does not self clear so after setting the bit it must be cleared 0 No reset 0x001E 2 S SYNC 1 to reset all output R dividers to the same state Table 14 110 0x0021 Input Clock ...

Page 89: ...02D Loss of Signal Time Value Reg Address Bit Field Type Setting Name Description 0x002D 1 0 R W LOS0_VAL_TIME Clock Input 0 0 for 2 msec 1 for 100 msec 2 for 200 msec 3 for one second 0x002D 3 2 R W LOS1_VAL_TIME Clock Input 1 same as above 0x002D 5 4 R W LOS2_VAL_TIME Clock Input 2 same as above 0x002D 7 6 R W LOS3_VAL_TIME Clock Input 3 same as above When an input clock is gone and therefore ha...

Page 90: ... Threshold Reg Address Bit Field Type Setting Name Description 0x0034 7 0 R W LOS3_TRG_THR 16 bit Threshold Value 0x0035 15 8 R W LOS3_TRG_THR ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 3 given a particular frequency plan Table 14 118 0x0036 0x0037 LOS0 Clear Threshold Reg Address Bit Field Type Setting Name Description 0x0036 7 0 R W LOS0_CLR_THR 16 bit...

Page 91: ...ble 14 122 0x0041 0x0044 LOS Pre Divider for IN0 IN1 IN3 FB_IN Reg Address Bit Field Type Setting Name Description 0x0041 4 0 R W LOS0_DIV_SEL A pre divider that is configured by ClockBuilder Pro 0x0042 4 0 R W LOS1_DIV_SEL A pre divider that is configured by ClockBuilder Pro 0x0043 4 0 R W LOS2_DIV_SEL A pre divider that is configured by ClockBuilder Pro 0x0044 4 0 R W LOS3_DIV_SEL A pre divider ...

Page 92: ...1 NVM bank has been burned by custom er 0x3F when 2 NVM banks have been burned by cus tomer When ACTIVE_NVM_BANK 0x3F the last bank has already been burned See 3 2 NVM Programming for a detailed description of how to program the NVM Table 14 125 0x00E3 Reg Address Bit Field Type Setting Name Description 0x00E3 7 0 R W NVM_WRITE Write 0xC7 to initiate an NVM bank burn Si5341 Si5340 Rev D Family Ref...

Page 93: ...CO_INTR Set by CBPro 0x00F7 5 R SMBUS_TIME_OUT_INTR Set by CBPro Table 14 129 0x00F8 Reg Address Bit Field Type Setting Name Description 0x00F8 3 0 R LOS_INTR Set by CBPro Table 14 130 0x00FE Device Ready Reg Address Bit Field Type Setting Name Description 0x00FE 7 0 R DEVICE_READY Ready Only byte to indicate device is ready When read data is 0x0F one can safely read write registers This register ...

Page 94: ...CE2 must be set to a value of 1 to force R0 to divide by 2 Note that the R0_REG value will be ignored while OUT0_RDIV_FORCE2 1 See R0_REG registers 0x0250 0x0252 for more information Table 14 133 0x0113 Clock Output Driver 0 Format Reg Address Bit Field Type Setting Name Description 0x0113 2 0 R W OUT0_FORMAT 0 Reserved 1 normal differential 2 Low Power differential 3 reserved 4 LVCMOS 5 7 reserve...

Page 95: ...Reserved 5 7 Reserved 0x0115 3 R W OUT0_VDD_SEL_EN Output Driver VDD Select Enable Set to 1 for normal operation 0x0115 5 4 R W OUT0_VDD_SEL Output Driver VDD Select 0 3 3V 1 1 8V 2 2 5V 3 Reserved 0x0115 7 6 R W OUT0_INV CLK and CLKb not inverted CLKb inverted CLK and CLKb inverted CLK inverted Each of the 4 output drivers can be connected to any of the N dividers More than 1 output driver can co...

Page 96: ...Address Bit Field Type Setting Name Description 0x013F 7 0 R W OUTX_AL WAYS_ON This setting is managed by CBPro during zero delay mode 0x0140 11 8 R W OUTX_AL WAYS_ON Table 14 138 0x0141 Reg Address Bit Field Type Setting Name Description 0x0141 5 R W OUT_DIS_LOL_MS K Set by CBPro 0x0141 7 R W OUT_DIS_MSK_LO S_PFD Set by CBPro Table 14 139 0x0145 Power Down All Outputs Reg Address Bit Field Type S...

Page 97: ... value 2 2 divider value 4 3 divider value 8 The following registers configure the P dividers which are located at the four input clocks seen in Figure 2 2 Si5340 Detailed Block Diagram on page 11 ClockBuilder Pro calculates the correct values for the P dividers Table 14 142 0x0208 0x020D P0 Dividers Reg Address Bit Field Type Setting Name Description 0x0208 7 0 R W P0 48 bit Integer Number 0x0209...

Page 98: ...Address Bit Field Type Setting Name Description 0x021C 7 0 R W P2 48 bit Integer Number 0x021D 15 8 R W P2 0x021E 23 16 R W P2 0x021F 31 24 R W P2 0x0220 39 32 R W P2 0x0221 47 40 R W P2 Table 14 147 0x0222 0x0225 P2 Divider Enable Set Reg Address Bit Field Type Setting Name Description 0x0222 7 0 R W P2_SET Set by CBPro 0x0223 15 8 R W P2_SET 0x0224 23 16 R W P2_SET 0x0225 31 24 R W P2_SET Si5341...

Page 99: ...s bit to cause a change to the P1 divider to take effect 0x0230 2 S P2_UPDATE Must write a 1 to this bit to cause a change to the P2 divider to take effect 0x0230 3 S P3_UPDATE Must write a 1 to this bit to cause a change to the P3 divider to take effect Bits 7 4 of this register have no function and can be written to any value Table 14 151 0x0235 0x023A M Divider Numerator Reg Address Bit Field T...

Page 100: ...CE2 0 then setting R0_REG 0 will disable the divider 0x0251 15 8 R W R0_REG 0x0252 23 16 R W R0_REG The final output R dividers are even dividers beginning with divide by 2 While all other values follow the formula in the bit description above divide by 2 requires an extra bit to be set For divide by 2 set OUT0_RDIV_FORCE2 1 See the description for register bit 0x0112 2 in this register map The R1...

Page 101: ...A12345 GM 12345 is the OPN unique identifier which sets OPN_ID0 0x31 OPN_ID1 0x32 OPN_ID2 0x33 OPN_ID3 0x34 OPN_ID4 0x35 0x0279 15 8 R W OPN_ID1 0x027A 23 16 R W OPN_ID2 0x027B 31 24 R W OPN_ID3 0x027C 39 32 R W OPN_ID4 Part numbers are of the form Si Part Num Base Grade Device Revision OPN ID Temp Grade Package ID Examples Si5340C A12345 GM Applies to a custom OPN Ordering Part Number device Thes...

Page 102: ... Bit Field Type Setting Name Description 0x27E 7 0 R W BaseLine ID An identifier for the device NVM without the frequency plan programmed into NVM Si5341 Si5340 Rev D Family Reference Manual Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 102 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Ch...

Page 103: ...ATE Must write a 1 to this bit to cause N0 divider changes to take effect Table 14 163 N Dividers for N1 N2 N3 Register Address Setting Name Size Same as Address 0x030D 0x0312 N1_NUM 48 bit Integer Number 0x0302 0x0307 0x0313 0x0316 N1_DEN 32 bit Integer Number 0x0308 0x030B 0x0318 0x031D N2_NUM 48 bit Integer Number 0x0302 0x0307 0x031E 0x0321 N2_DEN 32 bit Integer Number 0x0308 0x030B 0x0323 0x0...

Page 104: ...onds to MultiSynth N1 N_FSTEP_MSK 0x0339 1 Bit 2 corresponds to MultiSynth N2 N_FSTEP_MSK 0x0339 2 Bit 3 corresponds to MultiSynth N3 N_FSTEP_MSK 0x0339 3 There is one mask bit for each of the four N dividers Table 14 169 0x033B 0x0340 N0 Frequency Step Word Reg Address Bit Field Type Setting Name Description 0x033B 7 0 R W N0_FSTEPW 44 bit Integer Number 0x033C 15 8 R W N0_FSTEPW 0x033D 23 16 R W...

Page 105: ...4 bit Integer Number 0x033B 0x0340 0x034D 0x0352 N3_FSTEPW 44 bit Integer Number 0x033B 0x0340 Si5341 Si5340 Rev D Family Reference Manual Register Map Skyworks Solutions Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 105 Rev 1 3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice July 26 2021 105 ...

Page 106: ...host must write the IO_VDD_SEL configuration bit to the VDDA option This will ensure that both the host and the serial interface are operating at the optimum voltage thresholds The IO_VDD_SEL bit also affects the status pin levels and control pin thresholds When IO_VDD_SEL 0 the status outputs will have a VOH of 1 8 V When IO_VDD_SEL 1 the status outputs will have a VOH of 3 3 V When IO_VDD_SEL 0 ...

Page 107: ...onal used as a DCO Slightly lower output jitter may occur when the Phase Interpolator is bypassed 1 Bits in this field correspond to the N dividers as N3 N2 N1 N0 A soft reset reg 0x001C 0 should be asserted after changing any of these bits If it is expected that any of the N dividers will be changing from integer to fractional it is recommended that the corresponding bits be initialized to 0 so t...

Page 108: ...R W N_CLK_DIS Controls the clock to the N divider If an N divider is used the corresponding bit must be 0 N3 N2 N1 N0 See also registers 0x0A03 and 0x0A05 Table 14 182 0x0B57 Reg Address Bit Field Type Name Description 0x0B57 7 0 R W VCO_RESET_CAL CODE 12 bit value 0x0B58 11 8 R W VCO_RESET_CAL CODE Si5341 Si5340 Rev D Family Reference Manual Register Map Skyworks Solutions Inc Phone 781 376 3000 ...

Page 109: ...ceiver When the output amplitude needs to be different than standard LVDS or LVPECL the Common Mode Voltage settings must be set as shown in the table below No settings other than the ones in the table below are supported as the signal integrity could be compromised In addition the output driver should be ac coupled to the load so that the common mode voltage of the driver is not affected by the l...

Page 110: ...description for register 0x0141 Removed the User Scratch table Added table for registers 0x013F and 0x0140 Description and type added for P0 P1 P2 and P3 divider Enable Set tables Description added for table for M divider numerator Text below table for R0_REG updated Text added below Design_ID registers table to indicate User Scratch Removed tables about Nx_DELAY registers Description added for re...

Page 111: ...RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Skyworks products are not intended for use in medical lifesaving or life sustaining applications or other equipment in which the failure of the Skyworks products could lead to personal injury death physical or environmental damage Skyworks customers using or selling Skyworks products for use in such applications do so at the...

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