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4.1.2 Clock Input on XA/XB

An external clock can also be input on the XA/XB pins. Selection between the external crystal or clock is controlled by register
configuration. The internal crystal load capacitors (C

) are disabled in external clock mode. Because the input buffer at XA/XB is a

lower noise buffer than the buffers on IN2,1,0, a very clean input clock at XA/XB, such as a very high quality TCXO or XO, will, in some
cases, produce lower output clock jitter than the same input at IN2,1,0. If the XAXB input is unused and powered down then the XA
and XB inputs can be left floating. Note that ClockBuilder Pro will power down the XAXB input if it is selected as “unused”. If XAXB is
powered up but no input is applied then the XA input should be left floating and the XB input must be connected directly to ground. Both
a single-ended or a differential clock can be connected to the XA/XB pins as shown in the following figure:

Differential Connection

2xC

Single-ended XO Connection

Crystal Connection

OSC

XTA

2xC

2xCL

Si5341/40

Note: 2.0 Vpp_se max

XO with Clipped Sine

Wave Output

2xC

OSC

Si5341/40

Note: 2.0 Vpp_se max

CMOS/XO

Output

XO VDD

3.3 V

523 Ohms

2.5 V
1.8 V

0.1 µf

Single-ended Connection

Note: 2.5 Vpp diff max

OSC

475 Ohms

158 Ohms

422 Ohms

649 Ohms

866 Ohms

Figure 4.1. Crystal Resonator and External Reference Clock Connection Options

In addition to crystal operations, a clipped sine wave, CMOS, or differential reference clock is also accepted on the XA/XB interface.
Most clipped sine wave and CMOS TCXOs have insufficient drive strength to drive a 100 Ω or 50 Ω load. For this reason, place the
TCXO as close to the Si5340/41 as possible to minimize PCB trace length. In addition, ensure that both the Si5340/41 and the TCXO
are both connected directly to the ground plane. The above figure includes the recommended method of connecting a clipped sine
wave TCXO to the Si5340/41. Because the Si5340/41 provides DC bias at the XA and XB pins, the ~800 mV peak-peak swing can be
input directly into the XA interface of the Si5340/41 once it has been ac-coupled.

The above figure also illustrates the recommended method of connecting a CMOS rail-to-rail output to the XA/XB inputs. Because the
signal is single-ended, the XB input is ac-coupled to ground. The resistor network attenuates the rail-to-rail output swing to ensure that
the maximum input voltage swing at the XA pin is less than the data sheet specification. The signal is ac-coupled before connecting it to
the Si5340/41 XA input. Again, since the signal is single-ended, the XB input should be ac-coupled to ground.

If an external oscillator is used as the XAXB reference, it is important to use a low jitter source because there is effectively no jitter
attenuation from the XAXB pins to the outputs. To minimize jitter at the XA/XB pins, the rise time of the XA/XB signals should be as fast
as possible.

For best jitter performance, use a XAXB frequency above 40 MHz. Also, for XAXB frequencies higher than 125 MHz, the PXAXB
control must be used to divide the input frequency down below 125 MHz.

In most applications, using the internal OSC with an external crystal provides the best phase noise performance. See

AN905: External

References; Optimizing Performance

for more information on the performance of various XO's with these devices.

Si5341, Si5340 Rev D Family Reference Manual • Clock Inputs

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com

Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021