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SIS SIS8300-KU User Manual Download Page 87

Struck Documentation 

SIS8300-KU 

MTCA.4 Digitizer 

 

 

Page 87 of 92 

10.5.1 Interlock 

An interlock mechanism is implemented on the SIS8300-KU for operation with Vectormodu-
lator cards like the DWC8VM1 and DS8VM1. The OUT0 and OUT1 Zone 3 signals are 
generated from the logical combination of the backplane signals TX_19 (RF permit), RX_20 
(RF gate) and the FPGA ILOCK signals. 
 
The interlock scheme is shown in the diagram (courtesy of DESY) below. 
 

RF on

RF off

RF allowed

RF not allowed

RF_permit

Tx_19

(interlock 0)

RF_gate

Rx_20

(interlock 1)

FPGA

RTM Z3-ILOCK0

(0x12F)

FPGA

RTM Z3-ILOCK1

(0x12F)

RF on

RF off

RF on

RF off

FPGA

RTM Z3 ILOCK enable

(0x12F)

RTM (DWC8VM1)

AMC (SIS8300-KU)

OUT0

OUT1

enabled

not enabled

bit set

bit cleared

bit set

bit cleared

 
Interlock signals are available for SIS8300-KU with Zone 3 class compatibility A1.1CO only. 
Please refer to section 10.4.2. 
 
Please refer to application note "Interlock use with SIS8300-L and SIS8300-L2"  for 
additional information. It can be found on the Struck product DVD under: 
sisdvd_xxxxxx\sis8xxx and DWC\sis8300L2\doc\SIS8300-L_L2-AT-311214-1-V110-
Interlock.pdf 
 

SAFETY NOTE:

 make sure, that you have the proper interlock scheme for your application. 

Struck Innovative Systeme GmbH does not assume any liability for improper configuration. 
 
 

Summary of Contents for SIS8300-KU

Page 1: ...SIS8300 KU 10 channel 125 MSPS 16 bit MTCA 4 Digitizer User Manual SIS GmbH Harksheider Str 102A 22399 Hamburg Germany Phone 49 0 40 60 87 305 0 Fax 49 0 40 60 87 305 20 email info struck de http www...

Page 2: ...Chapter Firmware Options register updated Chapter RJ45 connector register updated Chapter SIS8900 RTM LVDS register updated Chapter Ordering Options updated Chapter Zone 3 connector schematic updated...

Page 3: ...2 Front Panel LEDs 18 4 3 SMD LEDs 19 5 Front panel 20 5 1 RJ45 LVDS In Outputs 21 5 2 SMA Clock Input 22 5 3 SFP Card Cage 22 6 Board Layout 23 7 Firmware Description 24 7 1 ADC Sample Logic 24 7 2...

Page 4: ...tion address upper 32bits 65 7 5 35 Read DMA Card Memory Source address 65 7 5 36 Read DMA Transfer length 66 7 5 37 Read DMA Control 66 7 5 38 Readout DMA Sample byte swap 67 7 5 39 Write DMA System...

Page 5: ...nd software for historical reasons i e remnants from the SIS8300_V2 and SIS8300L2 designs As we are aware that no manual is perfect we appreciate your feedback and will incorporate proposed changes an...

Page 6: ...4Gbit default DDR4 memory size ATxmega128A1U Microcontroller IPMI External Clock and Trigger Inputs Front panel digital I O 4in 4 out on RJ45 Connectors RTM ADC Analog Inputs I C Bus DAC Analog Output...

Page 7: ...nd Status Local I2C Bus Debug Management Bus Presence Detect Geographic Address TCLK ILOCK Isolation Control Power Control and Status JTAG Isolator Optional AMC_TCLK ILOCK JTAG Isolation Control FPGA...

Page 8: ...r can be uploaded via IPMI To upgrade in field you need an AVR programming tool i e AVR JTAGICE mkII After connecting to connector J32 please refer to section 3 3 the MMC can be upgraded using Atmel S...

Page 9: ...e looks like ipmitool I lan H IP MCH P B 0 b 7 T 0x82 t Slot raw 0x30 0x01 Flash Flash 0x00 Basic FLASH 0x01 Second FLASH Slot 0x72 1st slot 0x74 2nd slot 0x76 3rd slot Verification ipmitool I lan H I...

Page 10: ...Backplane and on board JTAG connector illustrated switch CON MTCA can be made via IPMI command IPMI command not implemented yet please request us for more information Upon power up the switch CON MTC...

Page 11: ...can be used to control the Vectormodulator on the DWC8VM1 Downconverter Vectormodulator RTM over the Zone 3 connector for example The two DAC channels can be routed to two front panel SMA outputs als...

Page 12: ...GA DAC Clock DS25CP152 select enable under MMC Control 7 6 5 4 4 5 6 1 2 1 2 RJ45 CLK 7 1 1 2 Inputs MUX D AD9510 2_CLK1 RTM_CLK1 AD9510 2_CLK2 MUX E AD9510 1_CLK1 RTM_CLK0 AD9510 1_CLK2 Outputs AD951...

Page 13: ...overview table is shown below Clock Usage RTM_CLK0 Ultra low jitter clock 1 ADC group 1 RTM_CLK1 Ultra low jitter clock 2 ADC group 2 RTM_CLK2 Clock switch yard RTM_CLK3 Not used RTM_CLK4 DAC Clock RT...

Page 14: ...RTM LVDS Test Input Output Control register please refer to section 7 5 32 The TCLKA or TCLKB selection and switch output control can be made per IPMI command IPMI raw 0x30 0x03 0xEC E 1 0 TCLK active...

Page 15: ...2 Gbe Port 0 Gbe Port 1 SI5338A Programmable Quad Output PLL controlled via I2C from FPGA 125 MHz 25 MHz quartz PCIe 3 Port 7 PCIe 2 Port 6 MGT REFCLK0 LLL low latency link Port 15 MGT REFCLK1 MGT REF...

Page 16: ...field JTAG firmware upgrades CON100 is a 2mm i e metric 14 pin header that allows you to reprogram the firmware of the SIS8300 KU board with a JTAG programmer The pin out is shown in the schematic be...

Page 17: ...at the left bottom side of the board The pin out is shown in the schematic below 3 4 J33 ATxmega128 Debug This 4 pin socket strip grants access to the debug port PE2 and PE3 of the ATxmega128 microcon...

Page 18: ...oard Power Good Off Off On Power Good FPGA loaded done signal module operational Typical module extraction process module handle pulled out blue red green Status Blink Off On Module still operational...

Page 19: ...designator LED comment Function D20A S1 Firmware dependent Optical Link 1 up D20B S2 Firmware dependent Optical Link 2 up D20C S3 Firmware dependent D20D S4 Firmware dependent D20E S5 Firmware depende...

Page 20: ...Struck Documentation SIS8300 KU MTCA 4 Digitizer Page 20 of 92 5 Front panel A sketch of the SIS8300 KU front panel view with front panel I O option is shown below...

Page 21: ...re shown in table below Pin Signal Name Function 1 C_P or D0_P Clock or Data 0 positive signal of differential pair 2 C_N or D0_N Clock or Data 0 negative signal of differential pair 3 D1_P Data 1 pos...

Page 22: ...he schematic of the input stage is shown below 5 3 SFP Card Cage The dual card cage is a zSFP type for best EMI protection and can host two SFP or SFP link media They can be enabled or disabled in the...

Page 23: ...8400A1 9000 CON301 DAC 1 Out JYEBAO SMA8400A1 9000 CON302 DAC 2 Out JYEBAO SMA8400A1 9000 CAGE105 SFP Cage 2 Ports TE Connectivity 1761014 1 J10 AdvancedMC JBT 16211701303000 J30 Zone 3 ERNI 973028 J3...

Page 24: ...ble ADC5 Clk DCO BUFG Delay 610ps ADC ch10 Trigger Block Threshold FIR data 4 clks delay ADC ch9 Trigger Block Threshold FIR data 4 clks delay Ch9 Gate Ch9 Trigger Pulse Ch10 data 16 1 Ch9 data 16 1 C...

Page 25: ...fifo_wr_en sis_write_64bit_addr_fifo_din sis_write_addr_fifo_wr_count Data Fifo 512 x 512 sis_write_data_fifo_wr_en sis_write_data_fifo_din sis_write_data_fifo_wr_count Write Interface DDR4 Memory Dat...

Page 26: ...ite_addr_fifo_din marked as sis_write_64bit_addr_fifo_din in the blockdiagram One write commands to the Data FIFO a valid sis_write_data_fifo_wr_en signal over one clock periods sis_write_fifo_wr_clk...

Page 27: ...x 256 bit Address Memory 8 bit byte Addresses 32 x 256 bit Address 0 x 1FFF FFFF 0 x 1FFF FFFE 0 x 1FFF FFF1 0 x 1FFF FFF0 0 x 000 000F 0 x 000 000E 0 x 000 0001 0 x 000 0000 0 x 3FFF FFFF 0 x 0000 0...

Page 28: ...register 1 0x16 R W Port 12 Link Control Status register 1 0x17 R W Port 13 Link Control Status register 1 0x18 R W Port 14 Link Control Status register 1 0x19 R W Port 15 Link Control Status register...

Page 29: ...ngth register 2 0x12B R W ADC chx Ringbuffer Delay register 0 to 2046 0x12F R W SIS8900 RTM LVDS Test Input Output Control register 0x200 R W DMA_READ_DST_ADR_LO32 0x201 R W DMA_READ_DST_ADR_HI32 0x20...

Page 30: ...3 15 8 0000FF00 RO Firmware Version 1 255 7 0 000000FF RO Firmware Revision 1 255 Example The initial versions of the SIS8300 KU reads 0x83031001 and 0x83032001 Meaning of the several firmware version...

Page 31: ...d 13 0 28 Clear reserved 12 0 27 Clear reserved 11 0 26 Clear reserved 10 0 25 Clear reserved 9 0 24 Clear reserved 8 0 23 Clear reserved 7 0 22 Clear reserved 6 0 21 Clear reserved 5 0 20 Clear reser...

Page 32: ...n features Bit read Function 31 reserved 30 16 Hardware Version flag 15 reserved 14 reserved 13 reserved 12 reserved 11 reserved 10 reserved 9 reserved 8 Z3 Class Bit 1 7 Z3 Class Bit 0 6 DUAL_OPTICAL...

Page 33: ...28 unused 0 27 unused 0 16 unused 0 15 unused 0 14 unused 0 13 Byte Read cycle 0 12 Byte Write cycle 0 11 Issue STOP condition 0 10 Issue REPEATSTART condition 0 9 Issue START condition 0 8 Master I...

Page 34: ...ess Link negotiated Speed bit 1 4 PCI Express Link negotiated Speed bit 0 3 PCI Express Link negotiated Width bit 3 2 PCI Express Link negotiated Width bit 2 1 PCI Express Link negotiated Width bit 1...

Page 35: ...ead 31 0 8 0 7 Status DDR4 Memory Init OK 6 0 5 Status internal Sample Logic Buffer FIFO Not Empty 4 Status internal Sample Logic Busy 3 0 2 1 Disable Sampling Reset Sample Logic 0 1 1 Arm Sampling St...

Page 36: ...channels can be disabled from storing data to memory by setting the corresponding disable bit in this register Bit write 31 12 11 Enable external Trigger 10 Enable internal Trigger 9 Disable Sampling...

Page 37: ...ble 14 LVDS Input 6 External Trigger Enable LVDS Input 6 External Trigger Enable 9 LVDS Input 1 External Trigger Enable LVDS Input 1 External Trigger Enable 8 LVDS Input 0 External Trigger Enable LVDS...

Page 38: ...falling edge 12 Input 0 External Trigger falling edge Input 0 External Trigger falling edge 11 Input 3 External Trigger Enable Input 3 External Trigger Enable 10 Input 2 External Trigger Enable Input...

Page 39: ...reset pulse 0 14 Receive logic reset pulse 0 13 Transmit logic enable Status of Transmit logic enable 12 Receive logic enable Status of Receive logic enable 11 Receive Link Status lane up 10 Receive...

Page 40: ...14 Receive logic reset pulse 0 13 Transmit logic enable Status of Transmit logic enable 12 Receive logic enable Status of Receive logic enable 11 Receive Link Status lane up 10 Receive Link Status cha...

Page 41: ...smit logic reset pulse 0 14 Receive logic reset pulse 0 13 Transmit logic enable Status of Transmit logic enable 12 Receive logic enable Status of Receive logic enable 11 Receive Link Status lane up 1...

Page 42: ...6 DMA Input Fifo read count D0 15 Transmit logic reset pulse 0 14 Receive logic reset pulse 0 13 Transmit logic enable Status of Transmit logic enable 12 Receive logic enable Status of Receive logic e...

Page 43: ...topped 4 DAC 1 Stop converting 1 DAC 1 stopped 3 DAC 2 Arm converting Start with next trigger Status DAC 2 Arm for trigger Wait for trigger 2 DAC 2 Start converting immediately Arm and Start Status DA...

Page 44: ...ter holds the two select bits for the 5 multiplexer chips as shown in the table below The assignment of the inputs to the resources i e clock inputs is listed in subsection 7 5 16 1 BIT access Name Fu...

Page 45: ...1 MUXAB_SEL Multiplexer C select lines Sel1 Sel0 Selected Input Net Name Clock source Description 0 0 EXT_CLKB0 Clock from RJ45 Connector CI1 4 IN front panel 0 1 EXT_CLKA0 Clock from SMA Connector CL...

Page 46: ...29 Set Function Output Level Status of Set Function Output Level 28 Select Function synchronisation CLK Status of Select Function synchronisation CLK 25 Status AD9510 2 24 AD9510 2 Select Bit Status A...

Page 47: ...the selected clock The clock selection is done via Bit 28 Function Syn CLK The actual function depends on the programming of the selected AD9510 1 1 Reserved Select Function synchronisation CLK Bit 28...

Page 48: ...e Bit 0 7 Address Data Byte Bit 7 Read Data Bit 7 MSB 1 Address Data Byte Bit 1 Read Data Bit 1 0 Address Data Byte Bit 0 Read Data Bit 0 LSB The power up default value is 0x0 Cmd Bit 1 Cmd Bit 0 Comm...

Page 49: ...p for details Bit Write read 31 unused Write Read Logic BUSY Flag 30 unused 0 29 unused 0 28 unused 0 27 unused 0 16 unused 0 15 unused 0 14 unused 0 13 Byte Read cycle 0 12 Byte Write cycle 0 11 Issu...

Page 50: ...CCLK Output Enable 14 Set Flash chip select CS Status Flash chip select 13 Set Block mode Status Block mode 12 Start command 0 11 Write buffer fifo command 0 10 Set Read Block mode Status Read Block...

Page 51: ...ap Delay value bit 1 22 Tap Delay value bit 0 21 DAC 2 Wrap select 20 DAC 1 Wrap select 19 18 FPGA CLK select FPGA CLK DAC Output Update Rate 0 125MHz ADC1 clock 1 250MHz 2 ADC1 clock 17 DAC Clock Mul...

Page 52: ...refer chapter 7 5 39 and onwards for future information s The DMA Data format corresponds to the DAC Data register format refer chapter 7 5 22 Note 3 It can be necessary to setup the tap delay to com...

Page 53: ...oduct DVD under sisdvd_xxxxxx sis8xxx and DWC sis8300L software tests rtm_i2c_test Please refer to the documentation of the respective RTM for details Bit Write read 31 unused Write Read Logic BUSY Fl...

Page 54: ...31 ADC Synch cmd Write Read Logic BUSY Flag 26 ADC Select Mux Bit 2 25 ADC Select Mux Bit 1 24 ADC Select Mux Bit 0 23 Read Cmd 22 not used 21 not used 20 not used 19 not used 14 not used 13 Address B...

Page 55: ...reserved Read Tap delay value Bit 6 17 reserved Read Tap delay value Bit 1 16 reserved Read Tap delay value Bit 0 15 reserved 0 14 reserved 0 13 reserved 0 12 ADC 9 10 Write Select Bit 11 ADC 7 8 Wri...

Page 56: ...CLK divider Bit 7 16 DAC 1 CLK divider Bit 0 DAC 1 CLK divider Bit 0 15 0 14 0 13 DAC 2 Enable external Trigger DAC 2 external Trigger enabled 12 DAC 2 Enable internal Trigger DAC 2 internal Trigger...

Page 57: ...ritten into the DAC RAM the last value is placed on address N 1 Bit write read 31 DAC 2 RAM endpoint Bit 15 DAC 2 RAM endpoint Bit 15 30 DAC 2 RAM endpoint Bit 14 DAC 2 RAM endpoint Bit 14 17 DAC 2 RA...

Page 58: ...Gap Time of the trapezoidal FIR filter Gap Time SumG Time Peaking Time Bit Function 31 Reserved 26 Enable Trigger 25 GT trigger condition 24 FIR Trigger Mode 0 Threshold Trigger 1 FIR Trigger 23 Puls...

Page 59: ...r the 10 ADC channels 7 5 28 2 1 Trigger Threshold FIR Trigger Mode 0 Bit 31 16 15 0 Function Threshold value OFF Threshold value ON default after Reset 0x0 A trigger output pulse is generated on two...

Page 60: ...calculation Trapezoidal value SUM2 SUM1 Where x P SUM1 Si i x x P sumG SUM2 Sj j x sumG The FIR filter logic generates the Trapezoidal by subtraction of the two running sums This implies that the inte...

Page 61: ...ample Start Block Address 25 1 256 bit blocks Don t care default after Reset 0x0 Explanation memory sample start block address The contents of the sample memory start block address register is assigne...

Page 62: ...25 1 0 reserved Sample Block Length 25 1 256 bit blocks Don t care default after reset 0x0 Sample Block Length value Number of samples of each channel waveform length 0x0 0x1 32 0x2 0x3 64 0x4 0x5 96...

Page 63: ...it D 9 RTM LVDS Output Bit D 9 18 RTM LVDS Output Bit D 8 RTM LVDS Output Bit D 8 17 RTM LVDS Output Bit D 7 RTM LVDS Output Bit D 7 16 RTM LVDS Output Bit D 6 RTM LVDS Output Bit D 6 15 0 14 0 13 0 1...

Page 64: ...er 2 8 5 and 10 3 2 Output signals of Interlock logic Out0 Out1 on Z3 connector are available in Z3 class A1 1CO only Please refer to chapter 10 3 2 and 10 4 1 Zone 3 TCLK select table RTM Z3 TCLK sel...

Page 65: ...Memory Source address define DMA_READ_SRC_ADR_LO32 0x202 This register holds the 32bit source byte address in the card s address space which is used to select the data source which is read from Bit 31...

Page 66: ...data bytes which is going to be transferred Bit 31 0 Function DMA Transfer length Note The DMA Transfer length must be a multiple of 64 Bytes 0x40 0x80 0xC0 7 5 37 Read DMA Control define DMA_READ_CT...

Page 67: ...ittle endian machines Example for disabled swapping Byte address offset Sample value 00 Sample 0 lo byte LSB 01 Sample 0 hi byte MSB 02 Sample 1 lo byte LSB 03 Sample 1 hi byte MSB Example for enabled...

Page 68: ...2 This register holds the 32bit destination byte address in the cards address space which is used to select the data source which is written to Bit 31 0 Function Card address space The address layout...

Page 69: ...RITE_CTRL 0x214 This register starts the Write DMA process and allows to poll the transfer status Bit write read 31 unused 0 0 1 unused 0 0 Start DMA DMA running 7 5 44 Write DMA maximal number of Out...

Page 70: ...IRQ_ENABLE 0x220 This register enables each interrupt source for interrupt generation The register is implemented as a J K register Bit write read 31 Disable User IRQ 0 30 Disable DAQ Done IRQ 0 29 un...

Page 71: ...IRQ happened 7 5 48 IRQ Clear define IRQ_CLEAR 0x222 This register clears any handled interrupts and allows the logic to generate new interrupts Bit write read 31 unused 0 0 16 unused 0 15 User IRQ cl...

Page 72: ...Struck Documentation SIS8300 KU MTCA 4 Digitizer Page 72 of 92 7 5 50 Memory test mode register define MEMORY_TEST_MODE_ REGISTER 0x230 Test functionality only not relevant for standard use...

Page 73: ...td_logic reg_0x400_0xFFF_adr 12bit wide addressbus which selects the next register to be read from or written to reg_0x400_0xFFF_wr_data 32bit wide databus which holds the data to be written to the ad...

Page 74: ...bits wide from user defined register logic A write request to the external register space causes the signals to change as follows The address and write data bus change their values to the current sel...

Page 75: ...o dma_bram_read_addr 32bit wide addressbus which is mapped over the 512MB of onboard sample RAM The addresses ranges from 0x00000000 to 0x1FFFFFFF 512MB dma_bram_read_en Optional Read enable pulse for...

Page 76: ...e of at least 1 clockperiod in length to trigger the interrupt logic If the driver user software has enabled the corresponding interrupt line an interrupt is generated on the PCIe interface user_irq_c...

Page 77: ...ive P6 PowerEnable low active P7 EEPROM Write Protect The EEPROM shall contain any relevant device information FRU records about the RTM refer to PICMG AMC 0 Additionally the EEPROM shall contain the...

Page 78: ...d and third way uses different LINUX tools which can be found on the product DVD 9 1 JTAG Firmware Upgrade procedure 1 Connect PC and SIS8300 KU CON100 with XILINX Platform cable USB device 2 Set Jump...

Page 79: ...ardware window selected configuration memory part appears Right click with mouse on s25fl128s device and select Program Configuration Memory Device In new dialog window please select configuration fil...

Page 80: ...t for each installed device one entry sis8300 0 e g Now the update can be started flashupdate path to file bin 9 3 Linux tool ipmitool The last from four methods of upgrading is to upload FPGA firmwar...

Page 81: ...out a power cycle of the crate A workaround is given in the command sequence below 1 Open a terminal and deactivate the Struck device driver sudo rmmod sis8300drv 2 Change into the root space sudo su...

Page 82: ...10 2 Ordering options The available part numbers are listed in the table below Struck part number Part name and configuration 05756 SIS8300 KU 8AC2DC DZ3 Channel 0 7 AC ADC Input Coupling 62MHz BW Ch...

Page 83: ...coupled transformer input stages In same fashion PA stands for DC coupled preamplifier input stage Col Row ef f e cd d c ab b a 10 GND CH0_PA CH0_PA GND GND GND GND CH0_TF CH0_TF 9 GND CH1_TF CH1_TF...

Page 84: ...AMC_TCLK AMC_TCLK 5 GND D8 D8 GND D7 D7 GND D6 D6 4 GND D5 D5 GND D4 D4 GND D3 D3 3 GND D2 D2 GND D1 D1 GND D0 D0 2 GND TMS TDI GND SCL MP 3 3V GND PWR 12V PWR 12V 1 GND TDO TCK GND SDA PS GND PWR 12V...

Page 85: ...igitizer Page 85 of 92 10 5 Note on AC DC input stage selection The AC transformer or DC operational amplifier input path is selected on the SIS8300 KU card via 0603 solder bridges as illustrated for...

Page 86: ...W61A ADC_CH1 1 SW61B ADC_CH1 2 SW58A ADC_CH2 2 SW58B ADC_CH2 3 SW56A ADC_CH3 3 SW56B ADC_CH3 4 SW53A ADC_CH4 4 SW53B ADC_CH4 5 SW51A ADC_CH5 5 SW51B ADC_CH5 6 SW48A ADC_CH6 6 SW48B ADC_CH6 7 SW46A ADC...

Page 87: ...M Z3 ILOCK0 0x12F FPGA RTM Z3 ILOCK1 0x12F RF on RF off RF on RF off FPGA RTM Z3 ILOCK enable 0x12F RTM DWC8VM1 AMC SIS8300 KU OUT0 OUT1 enabled not enabled bit set bit cleared bit set bit cleared Int...

Page 88: ...Struck Documentation SIS8300 KU MTCA 4 Digitizer Page 88 of 92 10 6 Zone 3 connector schematic...

Page 89: ...or profits whether in an action of contract negligence or other tortious action arising out of or in connection with the use or performance of this software 3 Claims for damages of any nature against...

Page 90: ...igger enable 56 Impedance 11 52 Internal trigger enable 56 Output Update Rate 51 RAM DMA write 52 Range 11 52 Repetition Wrap select 51 57 Software Trigger 43 Status 43 Tap delay 52 Test Mode Bit 52 T...

Page 91: ...I interface 46 clock distribution multiplexer control 44 Clock Multiplier IC SI5326 SPI interface 48 control 30 DAC control 51 DAC Data 52 DAC RAM endpoint register 57 DAC Trigger select and prescaler...

Page 92: ...zer Page 92 of 92 U222 45 U223 45 U240 45 U250 45 U251 45 U500 16 user LED 31 user blockram dma interface 75 user interrupt interface 76 Vectormodulator 11 Virtex 6 6 watchdog reset 16 Xilinx 6 78 XIL...

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