SIS SIS8300-KU, User Manual, Page: 55 / 92

Struck Documentation SIS8300-KU
MTCA.4 Digitizer
Page 55 of 92
7.5.25 ADC Input Tap delay register
#define SIS8300_ADC_INPUT_TAP_DELAY 0x49
The ADC input tap delay register is used to adjust the FPGA data strobe timing.
Bit
31-13 12 11 10 9 8 7-0
Function None ADC 9/10
Select
ADC 7/8
Select ADC 5/6
Select ADC 3/4
Select ADC 1/2
Select Write Tap
delay value
Bit
write read
31 reserved 0
...
28 reserved
27 reserved 0
26 ADC Read Select Mux Bit 2 0
25 ADC Read Select Mux Bit 1 0
24 ADC Read Select Mux Bit 0 0
23 reserved Read Tap delay value Bit 7
22 reserved Read Tap delay value Bit 6
.. ..
17 reserved Read Tap delay value Bit 1
16 reserved Read Tap delay value Bit 0
15 reserved 0
14 reserved 0
13 reserved 0
12 ADC 9/10 Write Select Bit
11 ADC 7/8 Write Select Bit
10 ADC 5/6 Write Select Bit
9 ADC 3/4 Write Select Bit
8 ADC 1/2 Write Select Bit
7 Write Tap delay value Bit 7 Write Tap delay value Bit 7
6 Write Tap delay value Bit 6 Write Tap delay value Bit 6
.. .. ..
1 Write Tap delay value Bit 1 Write Tap delay value Bit 1
0 Write Tap delay value Bit 0 Write Tap delay value Bit 0
The Write Tap delay value bits 7 downto 0 corresponds to IDELAY Tap delay value bits 8
downto 1 of the IDLEAY3 primitive of the Ultrascale (bit 0 is set 0).
No Tap delay is necessary with sample frequencies up to 125 MHz .