Struck Documentation
SIS8300-KU
MTCA.4 Digitizer
Page 26 of 92
7.2.1 Memory Write Interface
The Write Interface consists of the following signals:
write_fifo_wr_clk : in std_logic;
-- data: write fifo
write_data_fifo_wr_en : in std_logic;
write_data_fifo_din : in std_logic_vector(511 downto 0);
write_data_fifo_wr_count : out std_logic_vector(9 downto 0);
-- address: write fifo
write_addr_fifo_wr_en : in std_logic;
write_addr_fifo_din : in std_logic_vector(31 downto 0);
write_addr_fifo_wr_count : out std_logic_vector(9 downto 0);
A write cycle to the memory consists of one write command to the Address Fifo and one
write command to the Data Fifo.
One write command to the Address FIFO:
a valid “
sis_write_addr_fifo_wr_en
”
signal over one clock period
(sis_write_fifo_wr_clk)
along with
“write_addr_fifo_din” (marked as
“sis_write_64bit_addr_fifo_din” in the blockdiagram).
One write commands to the Data FIFO:
a valid “
sis_write_data_fifo_wr_en
” signal over one clock periods
(sis_write_fifo_wr_clk)
along with
“sis_write_data_fifo_din”.
When issuing a write command to the Address Fifo, the write command to the Data Fifo must
be issued no more than zero clock cycle later.
It is only allowed to write to the Address-FIFO, if “
sis_write_addr_fifo_wr_count
” is
lower than X”1FF” (not full).
It is only allowed to write to the Data-FIFO, if “
sis_write_data_fifo_wr_count
” is lower
than X”1FF” (not full).
The Memory Controller writes 512 bits (8 x 64 bits) to memory with one “write cycle”.
Therefore the lower 3 address bits of the written 64-bit address must be 0 and the “next
address” will be incremented by 8.
Note again:
the data width has changed from 256 bit to 512 bit with the SIS8300-KU and
therefore the logic has to write in packages of 512 bits (64 Bytes) into the
memory.