Struck Documentation
SIS8300-KU
MTCA.4 Digitizer
Page 44 of 92
7.5.16 Clock Distribution Multiplexer control register
#define SIS8300_CLOCK_DISTRIBUTION_MUX_REG
0x40
The SIS8300-KU has 5 IDT ICS853S057 clock multiplexer chips, which are labelled A to E
in the clock distribution scheme in section 2.8. The multiplexer control register holds the two
select bits for the 5 multiplexer chips as shown in the table below.
The assignment of the inputs to the resources (i.e. clock inputs) is listed in subsection
7.5.16.1.
BIT access Name
Function
31-12
FFFFF000
R/W
reserved
no
11-10
00000C00
R/W
MUXE_SEL
Multiplexer E select bits
9-8
00000300
R/W
MUXD_SEL
Multiplexer D select bits
7-6
000000C0
R/W
reserved
no
5-4
00000030
R/W
MUXC_SEL
Multiplexer C select bits
3-2
0000000C
R/W
MUXB_SEL
Multiplexer B select bits
1-0
00000003
R/W
MUXA_SEL
Multiplexer A select bits