SIS SIS8300-KU, User Manual, Page: 37 / 92

Struck Documentation SIS8300-KU
MTCA.4 Digitizer
Page 37 of 92
7.5.9 MLVDS Input/Output Control register
#define SIS8300_MLVDS_IO_CONTROL_REG 0x12
Bit
Write Read
31 Enable LVDS Output Bit 7 Enable LVDS Output Bit 7
30 Enable LVDS Output Bit 6 Enable LVDS Output Bit 6
.. .. ..
25 Enable LVDS Output Bit 1 Enable LVDS Output Bit 1
24 Enable LVDS Output Bit 0 Enable LVDS Output Bit 0
23 LVDS Output Bit 7 LVDS Output Bit 7
22 LVDS Output Bit 6 LVDS Output Bit 6
.. .. ..
17 LVDS Output Bit 1 LVDS Output Bit 1
16 LVDS Output Bit 0 LVDS Output Bit 0
15 LVDS Input 7 External Trigger Enable LVDS Input 7 External Trigger Enable
14 LVDS Input 6 External Trigger Enable LVDS Input 6 External Trigger Enable
.. .. ..
9 LVDS Input 1 External Trigger Enable LVDS Input 1 External Trigger Enable
8 LVDS Input 0 External Trigger Enable LVDS Input 0 External Trigger Enable
7 LVDS Input 7 External Trigger falling edge LVDS Input Bit 7
6 LVDS Input 6 External Trigger falling edge LVDS Input Bit 6
.. .. ..
1 LVDS Input 1 External Trigger falling edge LVDS Input Bit 1
0 LVDS Input 0 External Trigger falling edge LVDS Input Bit 0
Note: external trigger in signals are synchronized to the FPGA CLK05
The register related FPGA pins are connected via MLVDS transceivers to the RX/TX ports of
AMC multi-point bus. Assignment of register bits to AMC ports is shown in the table below.
AMC Port
LVDS Bit
TX20 7
RX20 6
TX19 5
RX19 4
TX18 3
RX18 2
TX17 1
RX17 0