Struck Documentation
SIS8300-KU
MTCA.4 Digitizer
Page 75 of 92
7.7 User Blockram DMA Interface
The User Blockram DMA interface consists of the following signals:
COMPONENT sis_pcie_intf
port (
..
dma_bram_clk : out std_logic; -- pcie user side clock
dma_bram_read_add_latency : in std_logic_vector(1 downto 0);
dma_bram_read_en : out std_logic;
dma_bram_read_addr : out std_logic_vector(31 downto 0);
dma_bram_read_data : in std_logic_vector(255 downto 0);
dma_bram_write_en : out std_logic;
dma_bram_write_addr : out std_logic_vector(31 downto 0);
dma_bram_write_data : out std_logic_vector(255 downto 0);
dma_bram_clk:
Free running 125MHz clock to which the data and control signals are synchronous to
dma_bram_read_addr:
32bit wide addressbus which is mapped over the 512MB of onboard sample RAM.
The addresses ranges from 0x00000000 to 0x1FFFFFFF (512MB)
dma_bram_read_en:
(Optional) Read enable pulse for connected logic. The read enable pulse is valid 1
clockperiod before the data is expected to be valid on the databus.
dma_bram_read_data:
256bit wide (due to PCIe endpoint design) databus which holds the data to be
transmitted over PCIe. The data needs to be valid 1 clockperiod after dma_bram_read_en
is valid.
Note:
This interface was built to be directly able to connect to a Xilinx CoreGen generated
blockram module with a 256bit wide read bus. Due to PCIe endpoint design constraints the
user has to read the blockram via DMA in 32byte steps.
Graphs (screenshots of the timings) and the description of the “dma_bram_write” bus will
come with the next update of the manual.