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SLG46140
19.0 Programmable Delay / Edge Detector
The SLG46140 has one programmable time delay logic cell available that can generate a delay that is selectable from one of four
timings (time1) configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay
patterns, rising edge detection, falling edge detection, both edge detection and both edge delay. These four patterns can be further
modified with the addition of delayed edge detection, which adds an extra unit of delay as well as glitch rejection during the delay
period. See the timing diagrams below for further information.
Note
:
The input signal must be longer than the delay, otherwise it will be filtered out.
19.1 Programmable Delay Timing Diagram - Edge Detector Output
Figure 78. Programmable Delay
Figure 79. Edge Detector Output
Programmable
Delay 0
OUT
IN
reg <489:488>
From Connection Matrix Output <43>
To Connection
Matrix Input <21>
reg <487:486>
reg <490>
Output Delay Control
Edge Mode Selection
Delay Value Selection
time1
Edge Detector
Output
IN
Rising Edge Detector
Falling Edge Detector
Both Edge Detector
Both Edge Delay
time1
time1 can be set by register value
