000-0046140-111
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SLG46140
18.0 Pipe Delay (PD)
The SLG46140 has one 16-stages DFF Pipe Delay Macrocell.
The Pipe Delay has three input signals from the matrix, Input (IN), Clock (CLK) and Reset (RST). The pipe delay cell is built from
16 D Flip-Flop logic cells that provide two delay options which are user selectable. The DFF cells are tied in series where the
output (Q) of each delay cell goes to the next DFF cell. The two outputs (OUT0 and OUT1) provide user selectable options for
1 – 16 stages of delay. There are delay output points for each set of the OUT0 and OUT1 outputs to a 4-input mux that is controlled
by register bits. The 4-input mux is used to control the selection of the amount of delay.
The overall time of the delay is based on the clock used in the SLG46140 design. Each DFF cell has a time delay of the inverse
of the clock time (either external clock or any Oscillator within the SLG46140). The sum of the number of DFF cells used will be
the total time delay of the Pipe Delay logic cell.
Figure 77. Pipe Delay
16 Flip-Flops
IN
RST
CLK
From Connection
Matrix Output <42>
From Connection
Matrix Output <41>
From Connection
Matrix Output <40>
reg <757:754>
reg <753:750>
To Connection
Matrix Input <20>
To Connection
Matrix Input <19>
OUT1
OUT0
reg <758>
0
1
