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Advanced Chipset Features
This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and
access to system memory resources, such as DRAM and the external
cache. It also coordinates communications between the conventional
ISA bus and the PCI bus. It must be stated that these items should
never need to be altered.
The default settings have been chosen because they provide the best
operating conditions for your system. The only time you might con-
sider making any changes would be if you discovered that data was
being lost while using your system.
DRAM Settings
The first chipset settings deal with CPU access to dynamic random
access memory (DRAM).
The default timings have been carefully chosen and should only be
altered if data is being lost.
Such a scenario might well occur if your system had mixed speed
DRAM chips installed so that greater delays may be required to pre-
serve the integrity of the data held in the slower memory chips.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing.
The Choice: 2, 3
