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SDRAM CAS Latency
SDRAM CAS Latency
SDRAM CAS Latency
SDRAM CAS Latency
SDRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field from
the default value specified by the system designer.
Ø
The Choice: 1.5, 2, 2.5 or 3.
Bank Interleave
Bank Interleave
Bank Interleave
Bank Interleave
Bank Interleave
The interleave number of internal banks, can be set to 2 way, 4 way
interleave or disabled. For VCM and 16Mb type dram chips, the bank
interleave is fixed at 2 way interleave.
When the dram timing is selected by SPD, it will be set by the value on
SPD of the RAM module(SDR).
Ø
The Choice: Disabled, 2 Bank, or 4 Bank.
Precharge to Active (Trp)
Precharge to Active (Trp)
Precharge to Active (Trp)
Precharge to Active (Trp)
Precharge to Active (Trp)
This item allows you to Precharge Command to Active Command
Period.
Ø
The Choice: 2T or 3T.
Active to Precharge (Tras)
Active to Precharge (Tras)
Active to Precharge (Tras)
Active to Precharge (Tras)
Active to Precharge (Tras)
This item allows you to Active Command to Precharge Command
Period.
Ø
The Choice: 6T or 7T.
Active to CMD (Trcd)
Active to CMD (Trcd)
Active to CMD (Trcd)
Active to CMD (Trcd)
Active to CMD (Trcd)
This item allows you to Active to CMD.
Ø
The Choice: 2T or 3T.
DRAM Command Rate
DRAM Command Rate
DRAM Command Rate
DRAM Command Rate
DRAM Command Rate
This item allows you to select the DRAM executed rate.
Ø
The Choice: 2T Command or 1T Command.
DRAM Burst Len
DRAM Burst Len
DRAM Burst Len
DRAM Burst Len
DRAM Burst Len
This item allows you to select Dram Burst Length.
Ø
The Choice: 4 or 8.
Write Recovery Time
Write Recovery Time
Write Recovery Time
Write Recovery Time
Write Recovery Time
This item allows you to select Write Recovery Time.
Ø
The Choice: 2T or 3T.
AGP & P2P Bridge Control
AGP & P2P Bridge Control
AGP & P2P Bridge Control
AGP & P2P Bridge Control
AGP & P2P Bridge Control
Options are in its sub-menu.
Press <Enter> to enter the sub-menu of detailed options.
