Shiratech Solutions Spark-100, Integration Manual, Page: 21 / 41

21 | Spark-100 HW user manual v1.3
Y2_P – Pin 20 Altera device –
REFCLK1LP – Pin P8 Reference clock for the transceivers
Y2_N – Pin 21 Altera device –
REFCLK1LN – Pin N8 Ref clock for the transceivers
Y3_P – Pin 20 SMARC interface -
PCIE_ - Pin S84 Clock out to carrier board
Y3_N – Pin 21 SMARC interface -
PCIE_B_REFCK- - Pin S85 Clock out to carrier board
Y4_P – Pin 26 Altera device –
CLK0P – Pin V11 FPGA clock input.
If a single ended clock is needed, use the P pin
only!
Y4_N – Pin 25 Altera device –
CLK0N – Pin W11 FPGA clock input.
Y5_P – Pin 29 Altera device –
CLK1P – Pin V12 FPGA clock input.
If a single ended clock is needed, use the P pin
only!
Y5_N – Pin 28 Altera device –
CLK1N – Pin W12 FPGA clock input.
Y6_P – Pin 32 Altera device –
CLK2P – Pin Y13 FPGA clock input.
If a single ended clock is needed, use the P pin
only!
Y6_N – Pin 33 Altera device –
CLK2N – Pin AA13 FPGA clock input.
Y7_P – Pin 35 Altera device –
CLK4P – Pin Y24 FPGA clock input.
If a single ended clock is needed, use the P pin
only!
Y7_N – Pin 36 Altera device –
CLK4N – Pin W24 FPGA clock input.
Note: If a single ended clock is required only the P line of the clock should be used.