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10 | Spark-100 HW user manual v1.3
Figure 5 - Bank 3B and 4A VCCPD is 2.5V
When the VCCPD is set to 2.5V, each I/O can be separately set to 1.5V, 1.8V or 2.5V. Figure 5 describes
two configurations in which the VCCPD is set to 2.5V.
In the top configuration Bank 3B's VCCIO is set to 2.5V and Bank 4A's VCCIO is set to 1.8V. In the bottom
configuration Bank 3B's VCCIO is set to 1.8V and Bank 4A's VCCIO is set to 1.5V.
2.1.4
Bank3A and Bank4A Vref
Bank3B and Bank4A can support an external DDR3 interface assembled on the carrier board. The DDR
requires reference voltage from the FPGA. These signals are available through the SMARC connector
VREF_3B (P104) and VREF_4B (P105).
If this option is not used these pins should be tied to ground.
2.2
Reset sources
The SPARK-100 supports three reset sources:
Cold reset (RESET_IN# – P127 on the SMARC interface)
o
Used to ensure the HPS is placed in a default state sufficient for software to boot
o
Triggered by a power-on reset and other sources e.g. push buttons on carrier board
o
Resets all HPS logic that can be reset
o
Affects all reset domains
o
This Reset is provided to the carrier board via P126
Warm reset (FORCE_RECOV# - S155 on the SMARC interface)
o
Occurs after HPS has already been through a cold reset
o
Used to recover system from a non-responsive condition
o
Resets a subset of the HPS state reset by a cold reset
o
Only affects the system reset domain, which allows debugging (including trace) to
operate through the warm reset
Debug Reset
o
Occurs after HPS has already been through a cold reset
o
Used to recover debug logic from a non-responsive condition
o
Only affects the debug reset domain
Programmable VCCPD
Bank 3B, 4A
2.5V, 3.3V 0.6A
ON
1
2
3
4
5
2.5 V
Programmable VCCIO
Bank 3B
1.5V, 1.8V, 2.5V, 3.3V 0.6A
Programmable VCCIO
Bank 4A
1.5V, 1.8V, 2.5V, 3.3V 0.6A
ON
1
2
3
4
5
ON
1
2
3
4
5
2.5 V
1.8 V
ON
1
2
3
4
5
1.5 V
1.8 V
Programmable VCCIO
Bank 3B
1.5V, 1.8V, 2.5V, 3.3V 0.6A
Programmable VCCIO
Bank 3B
1.5V, 1.8V, 2.5V, 3.3V 0.6A
Summary of Contents for Spark-100
Page 1: ...Spark 100 Altera Cyclone V SOC System on Module Integration guide Revision 1 3...
Page 35: ...35 Spark 100 HW user manual v1 3 Clock configuration...
Page 36: ...36 Spark 100 HW user manual v1 3 DDR setting...
Page 37: ...37 Spark 100 HW user manual v1 3...
Page 38: ...38 Spark 100 HW user manual v1 3...
Page 39: ...39 Spark 100 HW user manual v1 3...