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17 | Spark-100 HW user manual v1.3
Note: In some cases the SW handler will see the address space as a 7 bits range and so the address has
to shift right one bit to match.
2.3.7
SPI
The SPARK-100 supports up to two SPI interfaces. Each port offers:
Single CS signal for each SPI interface.
Programmable master serial bit rate up to 50 MHZ.
Serial master
Programmable data item size of 4 to 16 bits
Note – When the SPI interfaces are not in use, the pins can be configured as a GPIOs.
2.3.8
JTAG
The SPARK-100 integrates an optional on board 10 pins JTAG connector. The JTAG signals are also
connected to the SMARC connector, an analog switch selects between the JTAG connector and the
SMARC connector. The selection is done by a switch located on the SOM (SW3).
Ref.
Chip
I2C Port
Address A
Port
Address B
Description
Ux
PCA9548
0
1
1
1
0
0
0
0
RW
I2C Interface Expander
SMARC
0
1
1
1
0
0
0
0
RW
0
X
X
X
X
X
X
X
RW
I2C_CAM
0
1
1
1
0
0
0
0
RW
1
X
X
X
X
X
X
X
RW
I2C_GP
0
1
1
1
0
0
0
0
RW
2
X
X
X
X
X
X
X
RW
I2C_PM
0
1
1
1
0
0
0
0
RW
3
X
X
X
X
X
X
X
RW
I2C_LCD
Ux
TCA6416A
1
0
1
0
0
0
0
0
RW
20 H
I2C I/O Expander
Ux
Temp Sens
1
1
0
0
1
0
0
0
RW
48 H
Temperature Sensor
Ux
CLK_Gen
1
1
0
1
0
1
0
0
RW
54 H
Clock Generator
Ux
EEPROM
1
1
0
1
0
0
0
0
RW
50 H
EEPROM
Summary of Contents for Spark-100
Page 1: ...Spark 100 Altera Cyclone V SOC System on Module Integration guide Revision 1 3...
Page 35: ...35 Spark 100 HW user manual v1 3 Clock configuration...
Page 36: ...36 Spark 100 HW user manual v1 3 DDR setting...
Page 37: ...37 Spark 100 HW user manual v1 3...
Page 38: ...38 Spark 100 HW user manual v1 3...
Page 39: ...39 Spark 100 HW user manual v1 3...