11 | Spark-100 HW user manual v1.3
The cold and warm resets are controlled by voltage supervisors which guarantee the reset duration.
Both signals are available on the SMARC connector.
The FPGA can also be reset by the SOC ARM core or by an IO pin on the FPGA fabric.
When using the 128 MB QSPI Flash memory as a boot source the warm reset does not work
automatically due to configuration issues of the QSPI memory. For more details:
http://www.rocketboards.org/foswiki/Documentation/SocBoardQspiBoot
For 32MB QSPI Flash memory configuration the problem is resolved.
Summary of Contents for Spark-100
Page 1: ...Spark 100 Altera Cyclone V SOC System on Module Integration guide Revision 1 3...
Page 35: ...35 Spark 100 HW user manual v1 3 Clock configuration...
Page 36: ...36 Spark 100 HW user manual v1 3 DDR setting...
Page 37: ...37 Spark 100 HW user manual v1 3...
Page 38: ...38 Spark 100 HW user manual v1 3...
Page 39: ...39 Spark 100 HW user manual v1 3...