Shiratech Solutions Spark-100, Integration Manual, Page: 20 / 41

20 | Spark-100 HW user manual v1.3
The Clock distributor has two clock sources either the internal 25 MHz clock or an external clock from
the SMARC interface, the following table sum up the clock source options:
Clock input Clock source Remarks
SEC_REFP – Pin 11 SMARC interface
V5PCIE_ Pin P80 Reference clock from SMARC
connector
PRI_REFP – Pin 8 25Mhz internal
The selection between the clocks sources can be either automatic or using the REF_SEL pin (pin 6), the
selection is done via the I2C I/O expender(located on I2C1 of the HPS)see table below:
I/O
expender
port
Signal Type Description
0-2 REF_CLK_SEL
connected to Pin 6 of
the clock distributor Out Select the clock generator source.
"0" – Primary (internal)
"1" – Secondary
0-3 CLK_SYNC
connected to Pin 42 of
the clock distributor Out Synchronize the clock generator clocks
For the clock device
0-4 CLK_PDN
connected to Pin 43 of
the clock distributor Out Disable the clock generator(clock device)
"0" – Disable
"1" – Enabled
0-5
CLK_RESETN
connected to Pin 44 of
the clock distributor
Out
Reset the clock generator(clock device)
"0" – Reset
"1" – Normal
The CDCM6208 offers 8 clock outputs, the following table sums up the available out clocks of the device:
Clock output Clock destination Remarks
Y0_P – Pin 14 Altera device -
REFCLK0LP – Pin V5 Reference clock for the transceivers
Y0_N – Pin 15 Altera device - REFCLK0LN
– Pin V4 Reference clock for the transceivers
Y1_P – Pin 17 SMARC interface -
PCIE_ - Pin P83 Clock out to carrier board
Y1_N – Pin 16 SMARC interface
PCIE_A_REFCK- - Pin P84 Clock out to carrier board