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Sharp LH79524, User Manual

The Sharp LH79524 User Manual is a comprehensive guide designed to assist users in navigating and optimizing their LH79524 device. Packed with essential instructions and insights, this manual can be easily downloaded for free from our website, ensuring a hassle-free access to enriching product knowledge and functionalities.

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LH79524/LH79525 User’s Guide

Color Liquid Crystal Display Controller

Version 1.0

 4-25

11

IVS

Invert the Vertical Synchronization Signal

IVS selects the polarity of the LCDFP signal.

1 = LCDFP is active LOW
0 = LCDFP is active HIGH 

10:6

ACB

AC Bias Signal Frequency

ACB sets the frequency of the LCDEN signal.

STN modes: ACB applies to the CLCDC when it is operating in the STN mode. STN 
displays require periodic reversal of the pixel voltages in order to prevent damage to 
the STN panel due to DC charge accumulation. Program this field to select the required num-
ber of line clocks (the LCDLP signal) between each toggle of the AC bias signal (LCDEN).

ACB = (line clocks) – 1

TFT modes: This field has no effect if the CLCDC is operating in TFT mode because the 
LCDEN pin is instead utilized for a Data Enable signal.

5

///

Reserved

Reading returns 0. 

Write the reset value

.

4:0

PCD_LO

Panel Clock Divisor

Program this field and the PCD_HI field to select the LCD panel 

clock frequency (LCDDCLK frequency) from the input CLCDC CLOCK

 

frequency.

LCDDCLK = (CLCDC CLOCK)/(PCD+2)

Mono STN modes: LCDDCLK for mono STN panels with a four- (or eight-) bit interface 
should be programmed to be 1/4 (or 1/8) the desired individual pixel clock rate.

Color STN modes: Color STN displays receive multiple pixels during each clock cycle. The 
pixel data for Color STN displays is stored and transferred in packed format, with each pixel 
represented by three bits (R,G and B). Therefore, one byte contains the pixel data for 2 2/3 
pixels (RGB, RGB, RG) and three bytes contain the pixel data for eight complete pixels. For 
Color STN panels, each LCDDCLK cycle transfers one byte, containing 2 2/3 pixels, to the 
panel. LCDDCLK should be programmed to be as close as possible to 3/8 the desired indi-
vidual pixel clock rate. 

TFT mode: For TFT displays, the pixel clock divider can be bypassed by programming 
TIMING2:BCD = 1.

Table 4-19. TIMING2 Fields (Cont’d)

BIT

NAME

DESCRIPTION

Summary of Contents for LH79524

Page 1: ...LH79524 LH79525 User s Guide Version 1 0 ...

Page 2: ... PURPOSE ARE SPECIFICALLY EXCLUDED In no event will SHARP be liable or in any way responsible for any incidental or consequential economic or property damage Purchase of I2C components from SHARP Corporation or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights are granted to use these components in an I2C system provided that the system conforms to t...

Page 3: ...rface xli Chapter 10 I2S Converter xli Chapter 11 I O Configuration xli Chapter 12 Real Time Clock xli Chapter 13 Reset Clock Generation and Power Control xli Chapter 14 Synchronous Serial Port xli Chapter 15 Timers xlii Chapter 16 UARTs xlii Chapter 17 USB Device xlii Chapter 18 Vectored Interrupt Controller xlii Chapter 19 Watchdog Timer xlii Appendix Glossary xlii Chapter 1 Overview 1 1 Bus Arc...

Page 4: ...8 2 1 8 1 Brownout Interrupt 2 8 2 1 8 2 Pen Interrupt 2 9 2 1 8 3 End of Sequence Interrupt 2 9 2 1 8 4 FIFO Watermark Interrupt 2 9 2 1 8 5 FIFO Overrun Interrupt 2 9 2 1 9 Application Details 2 9 2 2 Register Reference 2 10 2 2 1 Memory Map 2 10 2 2 2 Register Descriptions 2 11 2 2 2 1 High Word Register HW 2 11 2 2 2 2 Low Word Register LW 2 13 2 2 2 3 Results Register RR 2 14 2 2 2 4 Interrup...

Page 5: ...4 3 4 3 1 Supported Displays and Panels 4 5 4 3 2 Frame Buffer 4 5 4 3 3 LCD DMA FIFOs 4 5 4 3 4 Pixel Serializer 4 6 4 3 5 How Pixels are Stored in Memory 4 6 4 3 6 Palette RAM 4 8 4 3 6 1 Grayscale Algorithm 4 9 4 3 6 2 Interrupts 4 9 4 3 6 3 LCD Panel Resolutions 4 9 4 3 7 LCD Data Multiplexing 4 12 4 3 8 LCD Interface Timing Signals 4 13 4 3 8 1 LCD Horizontal Timing Signals 4 13 4 3 8 2 LCD V...

Page 6: ... Register 2 ALITIMING2 4 41 4 6 Timing Waveforms 4 42 4 6 1 STN Horizontal Timing 4 42 4 6 2 STN Vertical Timing 4 42 4 6 3 TFT Horizontal Timing 4 42 4 6 4 TFT Vertical Timing 4 42 4 6 5 AD TFT HR TFT Horizontal Timing Waveforms 4 42 4 6 6 AD TFT HR TFT Vertical Timing Waveforms 4 42 Chapter 5 Direct Memory Access Controller 5 1 Theory Of Operation 5 2 5 1 1 Use for SSP and UART 5 3 5 1 2 Changin...

Page 7: ...p Back Mode 6 16 6 2 1 5 PHY Maintenance 6 17 6 2 1 6 Interrupts 6 17 6 3 Register Reference 6 18 6 3 1 Memory Map 6 18 6 3 2 Control Configuration And Status Register Definitions 6 20 6 3 2 1 Network Control Register NETCTL 6 20 6 3 2 2 Network Configuration Register NETCONFIG 6 22 6 3 2 3 Network Status Register NETSTATUS 6 24 6 3 2 4 Transmit Status Register TXSTATUS 6 25 6 3 2 5 Receive Buffer...

Page 8: ...use Frames TXPAUSEFM 6 48 6 3 4 Matching Registers 6 49 6 3 4 1 Hash Register Bottom HASHBOT 6 49 6 3 4 2 Hash Register Top HASHTOP 6 49 6 3 4 3 Specific Address 1 Bottom SPECAD1BOT 6 50 6 3 4 4 Specific Address 1 Top SPECAD1TOP 6 50 6 3 4 5 Specific Address 2 Bottom SPECAD2BOT 6 51 6 3 4 6 Specific Address 2 Top SPECAD2TOP 6 51 6 3 4 7 Specific Address 3 Bottom SPECAD3BOT 6 52 6 3 4 8 Specific Ad...

Page 9: ... DYNM2PRE 7 37 7 5 2 9 Dynamic Memory Self Refresh Exit Time Register REFEXIT 7 38 7 5 2 10 Dynamic Memory Last Data Out to Active Time Register DOACTIVE 7 39 7 5 2 11 Dynamic Memory Data In to Active Time Register DIACTIVE 7 40 7 5 2 12 Dynamic Memory Write Recovery Time Register DWRT 7 41 7 5 2 13 Dynamic Memory Active to Active Command Period Register DYNACTCMD 7 42 7 5 2 14 Dynamic Memory Auto...

Page 10: ...eory of Operation 9 2 9 1 1 Setting I2C Clock Timing 9 3 9 1 2 Interrupt Handling 9 4 9 1 3 Slave Mode 9 5 9 1 4 Master Mode 9 5 9 1 5 Resetting a Locked Slave 9 5 9 2 Register Reference 9 6 9 2 1 Memory Map 9 6 9 2 2 Register Definitions 9 7 9 2 2 1 I2C Configuration Register ICCON 9 7 9 2 2 2 I2C Slave Address Register ICSAR 9 8 9 2 2 3 I2 C Upper Slave Address Register ICUSAR 9 9 9 2 2 4 I2C Da...

Page 11: ...ESCTL3 11 6 11 2 2 5 Multiplexing Control 4 Register MUXCTL4 11 7 11 2 2 6 Resistor Configuration Control 4 Register RESCTL4 11 8 11 2 2 7 Multiplexing Control 5 Register MUXCTL5 11 9 11 2 2 8 Resistor Configuration Control 5 Register RESCTL5 11 10 11 2 2 9 Multiplexing Control 6 Register MUXCTL6 11 12 11 2 2 10 Resistor Configuration Control 6 Register RESCTL6 11 13 11 2 2 11 Multiplexing Control...

Page 12: ...ap 12 3 12 2 2 Register Descriptions 12 3 12 2 2 1 Data Register DR 12 3 12 2 2 2 Match Register MR 12 4 12 2 2 3 Load Register LR 12 4 12 2 2 4 Control Register CR 12 5 12 2 2 5 Interrupt Mask Set or Clear Register IMSC 12 5 12 2 2 6 Raw Interrupt Status Register RIS 12 6 12 2 2 7 Masked Interrupt Status Register MIS 12 6 12 2 2 8 Interrupt Clear Register ICR 12 7 Chapter 13 Reset Clock and Power...

Page 13: ...ar Register INTCLR 13 31 13 2 2 21 Core Clock Configuration Register CORECONFIG 13 32 13 2 2 22 System PLL Control Register SYSPLLCTL 13 33 13 2 2 23 USB PLL Control Register USBPLLCTL 13 34 Chapter 14 Synchronous Serial Port 14 1 Theory of Operation 14 1 14 1 1 Timing Waveforms 14 3 14 1 2 Motorola SPI Frame Format 14 4 14 1 3 Texas Instruments Frame Format 14 5 14 1 4 National Semiconductor Fram...

Page 14: ...15 2 2 11 Timer 1 Counter Register CNT1 15 19 15 2 2 12 Timer 1 Compare Registers T1CMPn 15 20 15 2 2 13 Timer 1 Capture Registers T1CAPn 15 21 15 2 2 14 Timer 2 Control Register CTRL2 15 22 15 2 2 15 Timer 2 Interrupt Control Register INTEN2 15 24 15 2 2 16 Timer 2 Status Register STATUS2 15 25 15 2 2 17 Timer 2 Counter Register CNT2 15 26 15 2 2 18 Timer 2 Compare Registers T2CMPn 15 27 15 2 2 1...

Page 15: ...terface 17 4 17 1 4 1 DMA Modes 17 4 17 1 4 2 DMA Bus Cycles 17 4 17 1 4 3 Bus Errors 17 4 17 1 5 DMA Operation 17 5 17 1 5 1 DMA Mode 0 OUT Endpoints 17 5 17 1 5 2 DMA Mode 0 IN Endpoints 17 5 17 1 5 3 DMA Mode 1 OUT Endpoints 17 6 17 1 5 4 DMA Mode 1 IN Endpoints 17 7 17 1 6 Remote Wakeup 17 7 17 2 Register Reference 17 8 17 2 1 Memory Map 17 8 17 2 2 Register Definitions 17 10 17 2 2 1 Function...

Page 16: ...Software Guidelines 18 4 18 2 Register Reference 18 5 18 2 1 Memory Map 18 5 18 2 2 Register Descriptions 18 6 18 2 2 1 IRQ Status Register IRQSTATUS 18 6 18 2 2 2 FIQ Status Register FIQSTATUS 18 7 18 2 2 3 Raw Interrupt Status Register RAWINTR 18 7 18 2 2 4 Interrupt Select Register INTSELECT 18 8 18 2 2 5 Interrupt Enable Register INTENABLE 18 8 18 2 2 6 Interrupt Enable Clear Register INTENCLE...

Page 17: ...C Operation 2 6 Figure 2 5 Use of the BATCNTL Pin 2 7 Chapter 3 Boot Controller Figure 3 1 Boot Controller Block Diagram 3 1 Figure 3 2 Active Pullup Circuit 3 5 Chapter 4 Color Liquid Crystal Display Controller Figure 4 1 LH79524 LH79525 LCD System Simplified Block Diagram 4 1 Figure 4 2 Block Diagram of a Typical Advanced LCD Panel 4 2 Figure 4 3 Color LCD Controller Block Diagram 4 4 Figure 4 4...

Page 18: ...sh 7 19 Figure 7 15 NAND Flash Timing Example 7 21 Chapter 9 I2 C Module Figure 9 1 I2C Module Block Diagram 9 1 Figure 9 2 I2 C Bus Protocol 9 2 Chapter 10 I2 S Converter Figure 10 1 I2S Converter Block Diagram 10 2 Figure 10 2 TI SSP Frame Format 10 3 Figure 10 3 I2S Format 10 3 Figure 10 4 Driving Latching Diagram 10 4 Figure 10 5 I2 S Master Mode Transmission Block Diagram 10 5 Figure 10 6 I2S...

Page 19: ...6 Microwire Frame Format Single Transfer 14 6 Figure 14 7 Microwire Frame Format Continuous Transfers 14 7 Chapter 15 Timers Figure 15 1 Timer Block Diagram 15 2 Figure 15 2 Count Clock Timing HCLK in Phase with CTCLK 15 3 Figure 15 3 Count Clock Timing HCLK not in Phase with CTCLK 15 3 Figure 15 4 Capture Signal Synchronization Timing 15 4 Figure 15 5 PWM Output Signal Timing 15 5 Chapter 16 UART...

Page 20: ...12 APB Peripheral Register Mapping 1 16 Chapter 2 Analog to Digital Converter Brownout Detector Table 2 1 ADC Register Summary 2 10 Table 2 2 HW Register 2 11 Table 2 3 HW Fields 2 11 Table 2 4 In Mux Definition 2 12 Table 2 5 LW Register 2 13 Table 2 6 LW Fields 2 13 Table 2 7 RR Register 2 14 Table 2 8 RR Fields 2 14 Table 2 9 IM Register 2 15 Table 2 10 IM Fields 2 15 Table 2 11 PC Register 2 1...

Page 21: ...Storage Format 31 16 4 6 Table 4 3 Frame Buffer Pixel Storage Format 15 0 4 7 Table 4 4 Palette Data Storage LH79525 with 12 Bit CLCDC 4 8 Table 4 5 Palette Data Storage LH79524 with 16 Bit CLCDC 4 8 Table 4 6 Supported TFT HR TFT and AD TFT LCD Panels 4 10 Table 4 7 Supported Color STN LCD Panels LH79524 only 4 10 Table 4 8 Supported Mono STN LCD Panels 4 10 Table 4 9 Color STN Intensities From G...

Page 22: ...elds 4 39 Table 4 47 ALITIMING1 Register 4 40 Table 4 48 ALITIMING1 Fields 4 40 Table 4 49 ALITIMING2 Register 4 41 Table 4 50 ALITIMING2 Fields 4 41 Chapter 5 Direct Memory Access Controller Table 5 1 DMA Controller Stream Assignments and Request Priority 5 1 Table 5 2 DMA Memory Map 5 5 Table 5 3 DMA Data Stream Register Summary One Set of Registers for Each of the Four Data Streams in Table 5 2...

Page 23: ...CTL Register 6 20 Table 6 7 NETCTL Fields 6 20 Table 6 8 NETCONFIG Register 6 22 Table 6 9 NETCONFIG Fields 6 22 Table 6 10 NETSTATUS Register 6 24 Table 6 11 NETSTATUS Fields 6 24 Table 6 12 TXSTATUS Register 6 25 Table 6 13 TXSTATUS Fields 6 25 Table 6 14 RXBQP Register 6 27 Table 6 15 RXBQP Fields 6 27 Table 6 16 TXBQP Register 6 28 Table 6 17 TXBQP Fields 6 28 Table 6 18 RXSTATUS Register 6 29...

Page 24: ...CCOL Fields 6 42 Table 6 54 TXUNDER Register 6 42 Table 6 55 TXUNDER Fields 6 42 Table 6 56 SENSERR Register 6 43 Table 6 57 SENSERR Fields 6 43 Table 6 58 RXRERR Register 6 44 Table 6 59 RXRERR Fields 6 44 Table 6 60 RXOVERR Register 6 44 Table 6 61 RXOVERR Fields 6 44 Table 6 62 RXSYMERR Register 6 45 Table 6 63 RXSYMERR Fields 6 45 Table 6 64 LENERR Register 6 45 Table 6 65 LENERR Fields 6 45 T...

Page 25: ...Silicon Version A 1 7 18 Table 7 4 16 bit Address Mapping 7 20 Table 7 5 32 bit Wide Data Bus Address Mapping SDRAM RBC 7 22 Table 7 6 32 bit Wide Data Bus Address Mapping SDRAM BRC 7 23 Table 7 7 16 bit Wide Data Bus Address Mapping SDRAM RBC 7 25 Table 7 8 16 bit Wide Data Bus Address Mapping SDRAM BRC 7 26 Table 7 9 Memory System Examples 7 27 Table 7 10 External Memory Controller Register Summ...

Page 26: ... 7 51 Table 7 51 DYNRASCASx Fields 7 51 Table 7 52 SCONFIGx Register 7 52 Table 7 53 SCONFIGx Fields 7 52 Table 7 54 SWAITWENx Register 7 54 Table 7 55 SWAITWENx Fields 7 54 Table 7 56 SWAITOENx Register 7 55 Table 7 57 SWAITOENx Fields 7 55 Table 7 58 SWAITRDx Register 7 56 Table 7 59 SWAITRDx Fields 7 56 Table 7 60 SWAITPAGEx Register 7 57 Table 7 61 SWAITPAGEx Fields 7 57 Table 7 62 SWAITWRx Re...

Page 27: ...0 2 CTRL Register 10 14 Table 10 3 CTRL Register Definitions 10 14 Table 10 4 WSINV Functionality 10 15 Table 10 5 STAT Register 10 16 Table 10 6 STAT Register Definitions 10 16 Table 10 7 IMSC Register 10 17 Table 10 8 IMSC Register Definitions 10 17 Table 10 9 RIS Register 10 18 Table 10 10 RIS Register Definitions 10 18 Table 10 11 MIS Register 10 19 Table 10 12 MIS Register Definitions 10 19 T...

Page 28: ... 11 33 RESCTL11 Fields 11 24 Table 11 34 MUXCTL12 Register 11 26 Table 11 35 MUXCTL12 Fields 11 26 Table 11 36 RESCTL12 Register 11 27 Table 11 37 RESCTL12 Fields 11 27 Table 11 38 RESCTL13 Register 11 29 Table 11 39 RESCTL13 Fields 11 29 Table 11 40 MUXCTL14 Register 11 30 Table 11 41 MUXCTL14 Fields 11 30 Table 11 42 MUXCTL15 Register 11 32 Table 11 43 MUXCTL15 Fields 11 32 Table 11 44 RESCTL15 ...

Page 29: ...le 12 5 MR Fields 12 4 Table 12 6 LR Register 12 4 Table 12 7 LR Fields 12 4 Table 12 8 CR Register 12 5 Table 12 9 CR Fields 12 5 Table 12 10 IMSC Register 12 5 Table 12 11 IMSC Fields 12 5 Table 12 12 RIS Register 12 6 Table 12 13 RIS Fields 12 6 Table 12 14 MIS Register 12 6 Table 12 15 MIS Fields 12 6 Table 12 16 ICR Register 12 7 Table 12 17 ICR Fields 12 7 Chapter 13 Reset Clock and Power Co...

Page 30: ... 13 31 PCLKSEL1 Fields 13 23 Table 13 32 SILICONREV Register 13 24 Table 13 33 SILICONREV Fields 13 24 Table 13 34 LCDPRE Register 13 25 Table 13 35 LCDPRE Fields 13 25 Table 13 36 LCDPRE Register Values 13 25 Table 13 37 SSPPRE Register 13 26 Table 13 38 SSPPRE Fields 13 26 Table 13 39 SSPPRE Register Values 13 26 Table 13 40 ADCPRE Register 13 27 Table 13 41 ADCPRE Fields 13 27 Table 13 42 ADCPR...

Page 31: ...CR Fields 14 20 Chapter 15 Timers Table 15 1 Timer 0 Register Summary 15 6 Table 15 2 Timer 1 Register Summary 15 6 Table 15 3 Timer 2 Register Summary 15 6 Table 15 4 CTRL0 Register 15 7 Table 15 5 CTRL0 Register Definitions 15 7 Table 15 6 CMP_CAP_CTRL0 Register 15 8 Table 15 7 CMP_CAP_CTRL0 Register Definitions 15 8 Table 15 8 INTEN0 Register 15 10 Table 15 9 INTEN0 Register Definitions 15 10 T...

Page 32: ...Register Summary 16 7 Table 16 3 UARTDR Register 16 8 Table 16 4 UARTDR Fields 16 8 Table 16 6 UARTRSR UARTECR Register Write Operations 16 9 Table 16 7 UARTRSR UARTECR Fields Write Operations 16 9 Table 16 5 Nine bit Mode Parity Bit Table 16 9 Table 16 8 UARTRSR UARTECR Register Read Operations 16 10 Table 16 9 UARTRSR UARTECR Fields Read Operations 16 10 Table 16 10 UARTFR Register 16 11 Table 1...

Page 33: ...e 17 12 UIR Register 17 14 Table 17 13 UIR Fields 17 14 Table 17 14 IIE Register 17 15 Table 17 15 IIE Fields 17 15 Table 17 16 OIE Register 17 16 Table 17 17 OIE Fields 17 16 Table 17 18 UIE Register 17 17 Table 17 19 UIE Fields 17 17 Table 17 20 FRAME1 Register 17 18 Table 17 21 FRAME2 Register 17 18 Table 17 22 FRAME1 Fields 17 18 Table 17 23 FRAME2 Fields 17 18 Table 17 24 INDEX Register 17 19...

Page 34: ...e 18 3 IRQSTATUS Register 18 6 Table 18 4 IRQSTATUS Fields 18 6 Table 18 5 FIQSTATUS Register 18 7 Table 18 6 FIQSTATUS Fields 18 7 Table 18 7 RAWINTR Register 18 7 Table 18 8 RAWINTR Fields 18 7 Table 18 9 INTSELECT Register 18 8 Table 18 10 INTSELECT Fields 18 8 Table 18 11 INTENABLE Register 18 8 Table 18 12 INTENABLE Fields 18 8 Table 18 13 INTENCLEAR Register 18 9 Table 18 14 INTENCLEAR Field...

Page 35: ...r Table 19 1 Watchdog Timer Memory Map 19 4 Table 19 2 CTL Register 19 5 Table 19 3 CTL Fields 19 5 Table 19 4 RST Description 19 6 Table 19 5 RST Field 19 6 Table 19 6 STATUS Description 19 7 Table 19 7 STATUS Fields 19 7 Table 19 8 COUNTx Description 19 8 Table 19 9 COUNTx Fields 19 8 ...

Page 36: ... LH79525 Please take a moment to read the Conventions and Terms section in its entirety Conventions and Terms For information on specific terms and acronyms see the Glossary in this User s Guide Unconnected Floating Inputs Many applications employing the LH79524 LH79525 require extremely low standby and operating current consumption especially in battery operated devices To achieve mini mum curren...

Page 37: ...hip but external to the core processor and its support devices are referred to throughout this User s Guide as blocks or Peripheral Devices The LH79524 LH79525 includes two buses an Advanced High Performance Bus AHB and an Advanced Peripheral Bus APB The devices shown on the APB in the block dia grams are an example of Peripheral Devices in this document Devices that are external to the chip are r...

Page 38: ...milarly not all bit fields in all registers can be written nor can all register bit fields yield useful information when read These restricted register bit fields will be specifically called out with three slashes and the word Reserved along with their special conditions in the bit field tables See Table 1 and Table 2 for examples of this practice NOTES RO Read Only WO Write Only RW Read and Write...

Page 39: ...as 0 Registers and bit fields with 0b1 values in all bits are referred to as set or as the binary hexadecimal or decimal value of the entire field or register When truth tables are used the 0b prefix is omitted for textual clarity Block Diagrams The functional descriptions in this User s Guide include block diagrams with symbols rep resenting logical or mathematical operations or selections usuall...

Page 40: ...ISTERNAME register Not all bit fields are named If a bit field has no name the Register is shown with numbers indicating the appropriate bit positions with the least significant bit on the right as in Figure 4 This bit ordering matches that of the Register tables shown in Table 1 Figure 2 Register with Bit Field Named LH7A404 92 OUTPUT REGISTERNAME BITFIELDNAME INPUT f Figure 3 Register with Multi...

Page 41: ...ammable parameters default memory widths address mapping and includes a register summary and register descriptions Chapter 3 Boot Controller This Chapter describes alternate booting options their use and configuration Also included is a programmer s model address mapping and a register summary and register descriptions Chapter 4 Color LCD Controller This Chapter describes the Color LCD Controller ...

Page 42: ...erial data in both master and slave mode The Chap ter includes a short overview a block diagram programmer s model interrupt channel list register summaries and register descriptions Chapter 11 I O Configuration This Chapter is an overview of the LH79524 LH79525 I O Configuration and pin multiplex ing The Chapter provides a block diagram programmer s model register summary and descriptions Chapter...

Page 43: ...25 USB Device beginning with a brief overview and including a block diagram programmer s model register summary and register descriptions Chapter 18 Vectored Interrupt Controller This Chapter describes the LH79524 LH79525 Vectored Interrupt Controller The Chapter includes a short overview a block diagram programmer s model interrupt channel list register summaries and register descriptions Chapter...

Page 44: ... Real Time Clock Watchdog Timer Pulse Width Modulators and an on chip Phase Locked Loop JTAG support is provided to simplify debugging Table 1 1 summarizes the differences in features between the LH79524 and the LH79525 All other peripherals and functional blocks are identical unless noted in the Chapter detail ing that block s function The block diagram for both devices appears in Figure 1 1 Refe...

Page 45: ...SUPPORT 10 20 MHz 32 768 kHz REAL TIME CLOCK COLOR LCD CONTROLLER EXTERNAL MEMORY CONTROLLER ADVANCED PERIPHERAL BUS BRIDGE ADVANCED HIGH PERFORMANCE BUS AHB ADVANCED PERPHERAL BUS APB BOOT ROM ADVANCED LCD INTERFACE 4 CHANNEL DMA CONTROLLER BOOT CONTROLLER GENERAL PURPOSE I O I O CONFIGURATION SYNCHRONOUS SERIAL PORT COUNTER TIMER 3 WATCHDOG TIMER I2 C 10 CHANNEL 10 BIT ADC WITH TSC and BROWNOUT ...

Page 46: ...upply An on chip 1 8 V to 3 3 V linear regulator can be used to generate the 1 8 V needed by the core logic 1 2 1 Linear Regulator When the linear regulator is enabled the 1 8 V power pins VDDC are outputs of the regulator This allows regulator operation verification In addition an external low ESR capacitor must be tied to the regulator output for stability If the regulator is disabled the 1 8 V ...

Page 47: ...k 1 Hz The 1 Hz Clock is derived by dividing the RTC OSC by 32 768 PLL System Clock CLK PLL 304 819 MHz This is the output from the System PLL The input for this clock is CLK OSC the System Oscillator Clock The minimum output frequency is 5 MHz USB PLL Clock USB PLL 304 819 MHz This is the output from the USB PLL the input is CLK OSC It can be programmed for any frequency between 5 MHz and 304 819...

Page 48: ...ce can be selected from HCLK or CLK OSC Counter Timer Clocks 25 415 MHz These clocks control the transition rates for the internal timers The source can be selected from HCLK or the External Timer input CTCLK Each timer is either clocked by CTCLK or HCLK divided by 2n 0 n 8 RTC Clock 32 768 kHz This clock controls the transition rate for the internal real time clock The source can be selected from...

Page 49: ... stall the core until the bus access is completed Programmers can use the three bus clocking modes to maximize throughput by reducing the re synchronization delays the number of wait states 1 3 1 1 Standard Bus Clocking Modes The Standard bus clocking modes are useful for designs involving low cost low speed memory where operation of the core at a faster speed than the AHB is desired These modes i...

Page 50: ...us Clocking Mode Designs involving frequent accesses of high speed memory may benefit by using the Fastbus Extension Mode This inherently synchronous mode clocks the core cache and AHB at the same frequency Where the Standard modes utilized two different clocks the Fastbus mode operates the core cache and AHB interface with two signals derived from the same source essentially the same clock Figure...

Page 51: ...ght out to an external pin nRESETOUT The nRESETOUT pin is held LOW for 8 HCLKs after HCLK becomes active following a system reset At power on reset nRESETIN the type of memory that the CPU boots from is determined by the state that PC7 PC6 PC5 and PC4 are externally connected to as shown in Table 1 3 If left undriven the default value is 0x0 as determined by internal pull down resistors If the CPU...

Page 52: ... the SoC is reset to ensure it exits the power up sequence in Normal Mode To ensure this an external AND gate is necessary to AND nTRST and nRESETIN Figure 1 4 illustrates the minimal circuit capable of guaranteeing the proper reset signals If the application will require a push button reset the circuit in Figure 1 5 is recommended Figure 1 4 Reset Circuit for TAP Controller LH79525 116 LH79524 LH...

Page 53: ... must never be left floating unconnected Each input must be pulled up or pulled down with a 33 kΩresis tor or smaller In addition to terminating input pins this also allows selecting the reset state of input pins using pull up logical 1 at reset or pull down logical 0 at reset resistors 1 4 2 2 Test Pins The two test pins TEST1 and TEST2 require being tied HIGH for the SoC to boot into Nor mal Ope...

Page 54: ... shows a schematic representation of one active pullup circuit One circuit is required for each PCx pin to be pulled high during reset nRESETOUT is presented to the Gate pin 1 of the P Channel FET When active LOW nRESETOUT causes the transistor to turn on and pull the PCx input HIGH When nRESETOUT transitions from LOW to HIGH at the end of the reset period the value on PC 7 4 is latched and the FE...

Page 55: ...h a 24 bit address and 16 32 bit data interface A 4 channel general purpose DMA controller All system resources accessible by the LH79524 LH79525 are memory mapped These include external resources e g ROM PROM SRAM SDRAM External Peripherals and internal resources system configuration registers peripheral configuration registers and internal memory The external memory space is partitioned into eig...

Page 56: ...t nDCS0 can be accessed from two locations 0x00000000 and 0x20000000 4 Programming REMAP to 10 will map internal SRAM to lower memory which means the same physical memory can be accessed from two locations 0x00000000 and 0x60000000 5 Programming REMAP to 11 will map external static memory Chip Select 0 to lower memory which means the same Chip Select nCS0 can be accessed from two locations 0x00000...

Page 57: ...T or I2C see Table 1 10 This override can be disabled by writing a 0 to the nCS1 Override bit CS1OV CS1O in the Boot Controller The override can be re enabled by writing a 1 to CS1OV CS1O If on system reset the boot configuration is set to 0bX0XX nCS1 remains mapped as described above and CS1OV CS1O has no effect on the memory map Table 1 7 SDRAM Memory Section Mapping START ADDRESS REMAP XX DEVIC...

Page 58: ...OM 0x48000000 0x4BFFFFFF Static Memory nCS2 0x4C000000 0x4FFFFFFF Static Memory nCS3 0x50000000 0x5FFFFFFF Invalid Access 0x60000000 0x7FFFFFFF Internal SRAM 0x80000000 0x80000FFF Boot ROM 0x80001000 0xFFFBFFFF Invalid Access Table 1 11 Primary AHB Peripheral Register Mapping ADDRESS RANGE DEVICE 0xFFFC0000 0xFFFE6FFF APB Bridge 0xFFFF7000 0xFFFF0FFF Invalid Access 0xFFFF1000 0xFFFF1FFF External M...

Page 59: ...I2S Converter 0xFFFC9000 0xFFFD8FFF Reserved 0xFFFD9000 0xFFFD9FFF GPIO Ports M N 0xFFFDA000 0xFFFDAFFF GPIO Ports K L 0xFFFDB000 0xFFFDBFFF GPIO Ports I J 0xFFFDC000 0xFFFDCFFF GPIO Ports G H 0xFFFDD000 0xFFFDDFFF GPIO Ports E F 0xFFFDE000 0xFFFDEFFF GPIO Ports C D 0xFFFDF000 0xFFFDFFFF GPIO Ports A B 0xFFFE0000 0xFFFE0FFF Real Time Clock 0xFFFE1000 0xFFFE1FFF DMA Controller 0xFFFE2000 0xFFFE2FFF...

Page 60: ...0T core in the LH79524 LH79525 includes an MMU that performs three pri mary functions It translates virtual addresses into physical addresses it enables cache and write buffering for particular ranges of virtual addresses and it controls memory access permissions When the MMU is turned off as it is at reset all virtual addresses are output directly onto the physical address bus the AHB The MMU sup...

Page 61: ...version automation function to minimize controller interrupt overhead Three power modes Off Standby and Run Brownout detector with interrupt 2 1 1 Operational Summary The ADC is an AMBA compliant SoC peripheral that connects as a slave to the APB The ADC block consists of an 10 channel 10 bit Analog to Digital Converter with integrated Touch Screen Controller The complete touch screen interface is...

Page 62: ...o 16 measurements in the sequence are stored in an entry in the Control Bank The mea surement sequence can be triggered by either software or a Pen Down Interrupt Figure 2 1 ADC Block Diagram LH79525 52 ANALOG BIAS AND CONTROL CLOCK GENERATOR CONTROL BANK STATE MACHINE oscen CLKSEL PWM 3 2 11 TO 1 MUX AN4 WIPER AN5 AN9 AN8 VREF AN3 LR Y AN2 IL Y AN7 AN6 VBAT AN1 UR X AN0 UL X A2DCLK DIGITAL EOSINT...

Page 63: ...t continuously software programs the HW and LW registers with the contents of the Idle High Word IHWCTRL and Idle Low Word ILWCTRL register values with the bias and ADC multiplexer settings until a new measurement sequence is triggered 2 1 2 Bias and Control Network The bias and control network supports 4 5 7 and 8 wire touch panels Multiplexers on the reference inputs enable connection in both si...

Page 64: ... 1 0 Figure 2 2 Bias and Control Network Block Diagram LH79525 53 11 TO 1 ANALOG MUX A D IN B12 PENIRQ B8 B7 B6 B4 B2 AVDD AVDD AVDD AVDD AN0 UL X B3 AN1 UR X B5 AN2 LL Y AN5 AN6 A3 TSCHWR 6 A2 TSCHWR 5 A1 TSCHWR 4 A0 TSCHWR 3 AN7 AN8 AN9 AN3 LR Y AN4 WIPER VREF B13 PENIRQ 100K 100K AVDD ...

Page 65: ...etector is an asynchronous comparator that compares a divided version of the 3 3 V supply and a bandgap derived reference voltage If the supply dips below a trip point the Brownout Detector sets a bit in the IS Register see Section 2 2 2 8 An interrupt is directly connected to the VIC This allows the SoC to notify peripherals of an impending shutdown and provides the ADC with time to save its stat...

Page 66: ... moves to the next bit down forces that bit HIGH and conducts another comparison The SAR control logic repeats this sequence until it reaches the least significant bit When the conversion is complete the N bit digital word is available in the register Figure 2 4 shows an example of a 4 bit conversion In this figure the y axis and the bold line show the DAC output voltage In this example 1 The firs...

Page 67: ...mal opera tion with BATCNTL LOW the voltage at VBAT is somewhere within the common mode input range of the ADC For example if the battery voltage is 6 V nominal choose R1 300 kΩ and R2 100 kΩ to give IN 1 5 V at a load of only 15 μA on the battery Note that the BATCNTL pin is only active when making the measurement on that particular ADC channel All other times BATCNTL is LOW Software can easily c...

Page 68: ...upt All five interrupts make up the combined interrupt TSCIRQ and presented to the VIC Each of the five individual maskable interrupts except Brownout is enabled or disabled by changing the mask bits in the IM Register see Section 2 2 2 4 Software can read the interrupt status bits through the IS Register even if corresponding mask bits are set see Section 2 2 2 8 Clearing the mask bits does not c...

Page 69: ...on the other hand the Pen detect circuit is disconnected there will be an edge every time the system enters Idle state 2 1 8 3 End of Sequence Interrupt The End of Sequence Interrupt occurs after the programmed number of conversions NOC occurs After the ADC converts all the data for a given sequence of conversions this interrupt goes HIGH The End of Sequence Interrupt is latched and remains HIGH u...

Page 70: ... Table 2 1 ADC Register Summary ADDRESS OFFSET NAME DESCRIPTION 0x00 HW High Word Register 0x04 LW Low Word Register 0x08 RR Results Register 0x0C IM Interrupt Masking Register 0x10 PC Power Configuration Register 0x14 GC General Configuration Register 0x18 GS General Status Register 0x1C IS Interrupt Status Register 0x20 FS FIFO Status Register 0x24 0x60 HWCB0 HWCB15 High Word Control Bank Regist...

Page 71: ... RO RO RO RO RO RO ADDR 0xFFFC3000 0x00 Table 2 3 HW Fields BITS NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 7 SETTIME Number of Clock Cycles Specifies the number of clock cycles that the ADC allows for the input signal to settle to within required accuracy before beginning conversion Used with bits 10 8 of the PC Register to set the acquire time in clock cycles see ...

Page 72: ...rsion 1 0 Table 2 4 In Mux Definition IN BIT6 BIT5 BIT4 BIT3 AN0 UL X 0 0 0 0 AN1 UR X 0 0 0 1 AN2 LL Y 0 0 1 0 AN3 LR Y 0 0 1 1 AN4 Wiper 0 1 0 0 AN5 0 1 0 1 AN6 0 1 1 0 AN7 0 1 1 1 AN8 1 0 0 0 AN9 1 0 0 1 VREF 1 0 1 0 VREF 1 0 1 1 VREF 1 1 0 0 VREF 1 1 0 1 VREF 1 1 1 0 VREF 1 1 1 1 ...

Page 73: ... RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD BIASCON REFM RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFC3000 0x04 Table 2 6 LW Fields BIT NAME DESCRIPTION 31 14 Reserved Reading returns 0 Write the reset value 13 2 BIASCON Bias Control These bits turn the FETs on and off as shown in Figure 2 2 The bit number corre...

Page 74: ...oldest entry from the result FIFO and increments the RDPTR Table 2 7 RR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD ADCOUT CBTAG RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFC3000 0x08 T...

Page 75: ...IM Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD INTEN BOIRQ PMSK EOSMSK FWMSK FOMSK RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW ADDR 0xFFFC3000 0x0C Table 2 10 IM Fields BIT NAME DESCRIPTION 31 7 ...

Page 76: ...O RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD BATLOC CLKSEL PWM REFEN BATEN NOC RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC3000 0x10 Table 2 12 PC Fields BIT NAME DESCRIPTION 31 15 Reserved Reading returns 0 Write the reset value 14 11 BATLOC Battery Measurement Location Program this field with the Channel number ...

Page 77: ...signals see Table 2 13 00 Turns off Power Mode and clock sets the BROWNOUT field bit 9 of the GS Register indicating that a brownout is detected even if VDDA_ADC is at the correct voltage 01 Standby wake on SSB or Pen Interrupt convert return clears the GS BROWNOUT bit even if VDDA_ADC is correct voltage 10 Run always on clears the BROWNOUT field bit 9 of the GS Register even if VDDA_ADC is at the...

Page 78: ...RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD FIFOWMK SSB SSM RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW ADDR 0xFFFC3000 0x14 Table 2 15 GC Fields BIT NAME DESCRIPTION 31 7 Reserved Reading returns 0 Write the reset value 6 3 FIFOWMK FIFO Watermark Programmed to values between 0 and 15 This value corresponds to watermark level...

Page 79: ... that reads the measurement results and determines whether the pen is still down If the pen is down the handler starts the timer for triggering the next measurement The handler discards the first set of measure ments taken during the initial Pen Down detection Otherwise the handler posts the current pen posi tion to some sort of OS queue Enable Pen Triggered Measurements to start the system Table ...

Page 80: ...7 6 5 4 3 2 1 0 FIELD BROWNOUT_UM PENSYNC_UM EOS_UM FWATER_UM FOVRN_UM RESET 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFC3000 0x1C Table 2 19 IS Fields BIT NAME DESCRIPTION 31 5 Reserved Reading returns 0 Write the reset value 4 BROWNOUT_UM Unmasked Brown Out Interrupt Status 1 Brown out Interrupt is active 0 Brown out Interrupt is not active 3 PEN...

Page 81: ... where the next measurement result will be stored 7 4 RDPTR Read Pointer FIFO Location Contains the index to the location in the result FIFO array where the next measurement result will be read Reads from the RR register increment this value 3 FFF FIFO Full 1 FIFO is full 0 FIFO is not full 2 FEMPTY FIFO Empty 1 FIFO is empty 0 FIFO is not empty 1 FOVRNDET FIFO Overrun Status Bit This bit is 1 whe...

Page 82: ...creen Y direction The same logic is used for the Control Bank Registers HWCBx and LWCBx The High Word Registers should contain The settling time The In bits The In bits The Ref bits The Low Word Registers should contain The bias control settings The Ref bits At the end of any given conversion a 4 digit Tag Number is stored in the FIFO along with the corresponding 10 bit output of the ADC For inter...

Page 83: ..._ID RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC3000 0xA4 Table 2 24 IHWCTRL Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 7 SETTIME_ID Idle Settling Time Specifies the delay in ADC clock cycles from when the state machine enters the Idle state to when the Pen Interrupt signal can be activated Prevents ...

Page 84: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD BIASCON_ID REFM_ID RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC3000 0xA8 Table 2 26 ILWCTRL Fields BIT NAME DESCRIPTION 31 14 Reserved Reading returns 0 W...

Page 85: ... 1 0 FIELD BROWNOUT PENSYNC EOSINTR FWATERINTR FOVRNINTR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFC3000 0xAC Table 2 28 MIS Fields BIT NAME DESCRIPTION 31 5 Reserved Reading returns 0 Write the reset value 4 BROWNOUT Brown Out Interrupt Status 1 Brown out Interrupt is asserted 0 Brown out Interrupt is not active or not enabled 3 PENSYNC Pen...

Page 86: ...terminate Table 2 29 IC Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET RW WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD BOIC PENIC EOSINTC RESET RW WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO ADDR 0xFFFC3000 0xB0 Table 2 30 IC Fields BITS NAME DESCRIPTION 31 3 Reserved Reading returns 0 Write the reset value 2 BOIC Bro...

Page 87: ...al boot pins at power on reset the Boot Controller supports Booting from 8 16 or 32 bit memory Configuration of the byte lane boot state for nCS1 Booting from alternate external devices e g NAND Flash UART I2C Figure 3 1 shows the Boot Controller block diagram Figure 3 1 Boot Controller Block Diagram REGISTER BLOCK nCS1 OVERRIDE AHB CONTROL TO nCS1 TO BOOT ROM BOOT CONTROL NAND FLASH nFRE nFWE FRO...

Page 88: ...is only visible in the memory map immediatly following reset When using small block devices the Boot Controller transfers 4KB of code from the boot device With large block devices the Boot Controller transfers 1KB This is because large block devices send an ECC value at the end of each page which would corrupt the code stream When using either type device but especially with large block devices la...

Page 89: ... Flash Small Block 16 bit 4 byte Address 0xD NAND Flash Small Block 16 bit 5 byte Address 0xE RESERVED RESERVED RESERVED 0xF RESERVED RESERVED RESERVED Table 3 2 Boot Configuration for Silicon Version A 1 PC 7 4 DEVICE TYPE DATA BUS WIDTH CONTROL 0x0 NOR Flash or SRAM 16 bit nBLEx LOW for Reads 0x1 NOR Flash or SRAM 16 bit nBLEx HIGH for Reads 0x2 NOR Flash or SRAM 8 bit nBLEx LOW for Reads 0x3 NO...

Page 90: ...23 signal for 8 bit A24 signal for 16 bit or A25 for 32 bit is HIGH nFWE is the active LOW signal to the NAND flash Write Enable pin This signal is the External Memory Controller s nWE signal enabled by address signal A23 A24 A25 nFWE is only active i e LOW when nWE is LOW and A23 A24 A25 is HIGH Gating these signals allows normal memory and I O accesses to other external devices to occur during e...

Page 91: ...E for the given transaction These address values differ depending on the NAND Flash device width being used NOTE Pins A3 and A4 carry different address signals depending on the width of the memory device For 8 bit devices Pin A3 Address signal A3 Pin A4 Address signal A4 For 16 bit devices Pin A3 Address signal A4 Pin A4 Address signal A5 For 32 bit devices Pin A3 Address signal A5 Pin A4 Address ...

Page 92: ...the device address that must be used is 0b1010000x This address is not alterable The Boot Con troller will always boot exactly 4Kbytes when using the I2C serial EEPROM Interface parameters are shown in Table 3 4 and the list of supported devices is shown in Table 3 5 Table 3 4 Boot Parameters for I2C PARAMETER VALUE Communication Speed 400 kHz Mode of SoC Master Mode Addressing Mode 7 bit I2 C EEP...

Page 93: ... in the table 3 2 Register Reference This section provides the Boot Controller register memory mapping and bit fields 3 2 1 Memory Map The base address for the Boot Controller is 0xFFFE6000 Table 3 7 summarizes the Boot Controller registers Table 3 6 UART0 Boot Parameters PARAMETER VALUE Protocol XMODEM Checksum Bit Rate 115 kbps Data Bits 8 Parity None Stop Bits 1 Packet Size 128 bytes Table 3 7 ...

Page 94: ... device from which the CPU is to boot Table 3 8 PBC Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PBC RESET 0 0 0 0 0 0 0 0 0 0 0 0 PC 7 4 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFE6000 0x00 Table 3 9 PBC Fields BITS NAME ...

Page 95: ... as 0 The very last thing Boot ROM software should do before returning control to the operating system is to write a 0 to this register so that normal routing of the nCS1 signal occurs NOTE Resets to the value to which PC 6 is externally driven during power on reset Table 3 10 CS1OV Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO...

Page 96: ...S2EP CS1EP CS0EP RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 RW RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW ADDR 0xFFFE6000 0x08 Table 3 13 EPM Fields BITS NAME DESCRIPTION 31 4 Reserved Reading returns 0 Write the reset value 3 CS3EP nCS3 Configured for External Peripherals 1 All burst accesses to nCS3 are converted to a series of non sequential single transfers 0 Accesses to nCS3 are unaltered 2 C...

Page 97: ...vides all necessary control and data signals to interface the SoC directly to a variety of color and monochrome LCD panels including STN and TFT panels The ALI modifies the CLCDC output to allow the chip to connect directly to the Row and Column driver chips on superthin panels including AD TFT HR TFT or any panel that supports this method of connection Figure 4 1 shows a simplified diagram of the...

Page 98: ...panel s power supplies and illuminator Including these devices in STN and TFT panels however comes at the cost of bulk and weight The ALI eliminates the need for a separate Timing ASIC since it is able to drive the panel s Row and Column driver chips directly The DC DC conversion is also handled off panel by a separate device operating the panel s high voltage supplies and illuminator The DC DC co...

Page 99: ...r TFT panel The following parameters can be programmed in the CLCDC Horizontal front and back porch width Horizontal synchronization pulse width Number of pixels per line Vertical front and back porch width Vertical synchronization pulse width Number of horizontal lines per panel Number of panel data clocks per line Programmable signal polarities active HIGH or active LOW AC panel bias Panel data ...

Page 100: ...CK GENERATOR TIMING CONTROLLER CONTROL AND STATUS REGISTER UPPER PANEL FORMATTER UPPER PANEL OUTPUT FIFO STN TFT DATA SELECT UPPER STN DATA LCD PANEL CLOCK LCD PANEL CONTROL INPUT FIFO CONTROL PIXEL SERIALIZER PALETTE 128 32 GRAY SCALER CLCDCLK UPPER PANEL DMA FIFO LOWER PANEL DMA FIFO LOWER PANEL FORMATTER INTERRUPT GENERATION INTERRUPTS LOWER PANEL OUTPUT FIFO LOWER STN DATA TFT DATA FIFO UNDERF...

Page 101: ...imings required to drive Single monochrome panels Dual monochrome panels Color LCD panels Super Twisted Nematic STN displays Active Thin Film Transistor TFT LCD displays 4 3 2 Frame Buffer A set of numbers representing the color or gray scale of each pixel the CLCDC displays is stored in a region of static memory called a frame buffer The CLCDC uses its DMA Con troller to fetch data from the frame...

Page 102: ...word cor responding to the bpp combinations The required data for each panel display pixel must be extracted from the data word The first pixel value in the frame corresponds to the color value encoded in P0 see Table 4 3 the second corresponds to P1 the third to P2 and so on continuing in Table 4 2 NOTES 1 LH79525 with 12 Bit CLCDC 2 LH79524 with 16 Bit CLCDC Table 4 1 Pixel Display Arrangement p...

Page 103: ...er Pixel Storage Format 15 0 BPP DMA FIFO OUTPUT BITS 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 2 p7 p6 p5 p4 p3 p2 p1 p0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 4 p3 p2 p1 p0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 8 p1 p0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 121 p0 11 10 9 8 7 6 5 4 3 2 1 0 162 p0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 104: ...ata NOTE Blue and red palette data can be swapped by programming CTRL BGR NOTE Blue and red palette data can be swapped by programming CTRL BGR Table 4 4 Palette Data Storage LH79525 with 12 Bit CLCDC BIT NAME DESCRIPTION 31 Unused 30 27 MB 3 0 Most Significant Blue palette data 26 Unused 25 22 MG 3 0 Most Significant Green palette data 21 Unused 20 17 MR 3 0 Most Significant Red palette data 16 1...

Page 105: ...n for the LCD panel s RGB data pattern 4 3 6 2 Interrupts The CLCDC has four individually maskable interrupt conditions associated with a single combined interrupt The single combined interrupt is asserted if any of the combined inter rupt conditions are asserted and unmasked 4 3 6 3 LCD Panel Resolutions LCD panel resolution is expressed as the total number of horizontal pixels multiplied by the ...

Page 106: ...zed 256 colors selected from 65 536 available colors 12 Direct 4 4 4 RGB 1 16 Direct 5 5 5 RGB Intensity The Intensity bit can be unused or it can be used to connect to the LSB of the R G and B components of a 6 6 6 TFT panel 2 Table 4 7 Supported Color STN LCD Panels LH79524 only BPP SOURCE COLOR STN SINGLE AND DUAL PANEL 8 BIT BUS NOTE 1 Palletized 2 colors selected from 3 375 available colors 1...

Page 107: ...1 Duty cycle is determined by pixels on pixels on pixels off 2 Resulting intensity 000 black 100 white Table 4 9 Color STN Intensities From Gray Scale Modulation 4 BIT PALETTE VALUE DUTY CYCLE1 RESULTING INTENSITY2 0b0000 0 90 00 0 0b0001 10 90 11 1 0b0010 18 90 20 0 0b0011 24 90 26 7 0b0100 30 90 33 3 0b0101 36 90 40 0 0b0110 40 90 44 4 0b0111 45 90 50 0 0b1000 45 90 50 0 0b1001 50 90 55 6 0b1010...

Page 108: ...INGLE PANEL DUAL PANEL SINGLE PANEL DUAL PANEL SINGLE PANEL DUAL PANEL SINGLE PANEL C2 LCDVD15 MUSTN0 MUSTN0 MUSTN0 MUSTN0 CUSTN0 CUSTN0 INTENSITY C1 LCDVD14 X X X MLSTN4 X CLSTN4 BLUE4 C10 LCDVD13 X X MUSTN6 MUSTN6 CUSTN6 CUSTN6 BLUE3 A10 LCDVD12 X X X MLSTN7 X CLSTN7 BLUE2 A11 LCDVD11 X X X MLSTN6 X CLSTN6 BLUE1 B10 LCDVD10 X X X MLSTN5 X CLSTN5 BLUE0 C9 LCDVD9 X MLSTN3 X MLSTN3 X CLSTN3 GREEN4 ...

Page 109: ...l external hardware required except for Continuous Grain Silicon CGS panels 4 3 8 1 LCD Horizontal Timing Signals The horizontal components of LCD timing describe the process of writing one line of LCD data to a LCD panel and include programmable delays before and after the data is written to the panel A line of data is composed of all pixel information for one displayed line See Section 4 6 for t...

Page 110: ...ls Data is written to an LCD panel in frames Each frame is composed of a number of hori zontal lines The vertical components of LCD timing describe the process of writing one full frame to an LCD panel Each frame begins with a frame pulse or vertical synchronization pulse of programmable duration Each frame pulse is followed by a programmable delay the vertical back porch When the vertical back po...

Page 111: ...ed the LSI drivers in the panel can latch and the display will freeze Typically when this happens the colors will be incorrect on STN panels In addition the power down sequence must be fol lowed or LCD life can be degraded Figure 4 4 is an example of these timing requirements for the SHARP LM057QCTT03 Color STN LCD Panel and the accompanying timing specifications Always refer to your specific LCD ...

Page 112: ...image on HR TFT and AD TFT LCD panels software should write a complete frame of all 1s white to the LCD just prior to initiating the turn off sequence To minimize the appearance of a retained image on a TFT LCD panel software should write a complete frame of all 0s black just prior to initiating the turn off sequence In all cases the illumination source should be turned off prior to initiating the...

Page 113: ...I is programmed via its16 bit APB interface and receives control signals and display data from the CLCDC The ALI converts the display data to a format suitable for direct con nection to the Row and Column driver ICs in AD TFT HR TFT displays or any display using similar technology Figure 4 5 ALI Simplified Block Diagram LH79525 45 ROUTER DATA AND CONTROL SIGNALS FROM CLCDC ADVANCED PERIPHERAL BUS ...

Page 114: ...led and the ALI Control Register can be used The ALI generates the MOD signal automatically By default activation of MOD occurs 2 SPS rising edge clocks after activation of the controller This can be reprogrammed for a longer or shorter wait or can be overridden via the ALI Control Register 4 4 2 ALI Operating Modes The ALI has two operating modes Bypass Mode or Active Mode The ALI Setup Register ...

Page 115: ...ary ADDRESS OFFSET NAME DESCRIPTION 0x000 TIMING0 Horizontal Axis Timing Control 0x004 TIMING1 Vertical Axis Timing Control 0x008 TIMING2 Clock and Signal Polarity Control Register 0x00C Reserved Do not access 0x010 UPBASE Upper Panel Frame Buffer Base Address Register 0x014 LPBASE Lower Panel Frame Buffer Base Address Register 0x018 INTREN Interrupt Enable Register 0x01C CTRL Panel Parameters Pan...

Page 116: ... to 256 pixel clock cycles HBP LCDDCLK periods 1 23 16 HFP Horizontal Front Porch HFP specifies the number of LCDDCLK periods between the end of valid data and the beginning of the LCDLP signal HFP can be programmed for a delay of 1 to 256 pixel clock cycles HFP LCDDCLK periods 1 15 8 HSW Horizontal Synchronization Pulse Width HSW specifies the width of the LCDLP signal in LCDDCLK periods In STN m...

Page 117: ...nterface The data path latency forces some restrictions on the usable minimum values for horizontal porch width in STN Mode The minimum values are HSW 2 and HBP 2 Single Panel Mode HSW 3 HBP 5 HFP 5 Panel Clock Divisor PCD 1 CLCDCLK 3 Dual Panel Mode HSW 3 HBP 5 HFP 5 PCD 5 CLCDCLK 7 If sufficient time is given at the start of the line for example setting HSW 6 HBP 10 data will not get corrupted f...

Page 118: ... to 255 additional line clock cycles TFT modes The VBP delay begins after the vertical synchronization signal for the previous frame LCDFP has been deasserted STN modes Program to zero The vertical back porch is not programmable and always a duration of zero Programming any other value other than zero will have no effect 23 16 VFP Vertical Front Porch VFP defines the number of inactive lines at th...

Page 119: ...o an odd number of lines for AD TFT and HR TFT panels AD TFT and HR TFT displays utilize the LCDREV signal as an AC bias signal it does not alter LCDDCLK The LCDREV signal os cillates driven HIGH during one frame and driven LOW during the next frame To avoid long term LCD damage the AC bias applied to any line of an LCD panel should average to a net 0 VDC When correctly programmed the LCDREV signa...

Page 120: ... the pixel clock divider logic 0 Use the pixel clock divider logic See the description of the PCD bit field below 25 16 CPL Clocks Per Line CPL specifies the number of LCDDCLK pulses fed to the LCD panel during each horizontal line The TIMING2 CPL and TIMING0 PPL fields work together both must be programmed correctly in order for the CLCDC to function correctly Actual Pixels Per Line APPL 16 x TIM...

Page 121: ... 4 0 PCD_LO Panel Clock Divisor Program this field and the PCD_HI field to select the LCD panel clock frequency LCDDCLK frequency from the input CLCDC CLOCK frequency LCDDCLK CLCDC CLOCK PCD 2 Mono STN modes LCDDCLK for mono STN panels with a four or eight bit interface should be programmed to be 1 4 or 1 8 the desired individual pixel clock rate Color STN modes Color STN displays receive multiple...

Page 122: ...rrent registers at each LCD vertical synchronization This event causes the BUI bit and an optional interrupt to be gen erated The BUI bit indicates that it is safe to update both the UPBASE and LPBASE Reg isters The interrupt can be used to reprogram the base address when generating double buffered video Table 4 20 UPBASE Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD LCDUPBASE...

Page 123: ...each LCD vertical synchroniza tion This event causes the BUI bit and an optional interrupt to be generated The BUI bit indicates that it is safe to update both the UPBASE and LPBASE Registers The interrupt can be used to reprogram the base address when generating double buffered video Table 4 22 LPBASE Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD LCDLPBASE RESET 0 0 0 0 0 0 0...

Page 124: ...O RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD MBEIEN VCIEN BUIEN FUIEN RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFF4000 0x18 Table 4 25 INTREN Fields BIT NAME DESCRIPTION 31 5 Reserved Reading returns 0 Write the reset value 4 MBEIEN Bus Master Error Interrupt Enable 1 Interrupt enabled 0 Interrupt disabled 3 VCIEN Verti...

Page 125: ... programming the INTREN VCIEN bit to 1 2 Program the CTRL LCDEN bit to 0 The controller will complete the current frame before sampling this bit 3 Wait for the Vertical Compare Interrupt Upon assertion of the interrupt program the new mode e g from color to monochrome using the CTRL BW bit Then program the CTRL LCDEN bit to 1 and clear the Vertical Compare Interrupt by writ ing a 1 to the STATUS V...

Page 126: ... regardless of the setting of the PWR bit 1 LCD power ON 0 LCD power OFF 10 BEPO Big Endian Pixel Ordering The BEPO bit selects between little and big endian pixel packing for 1 2 and 4 bpp display modes The BEPO bit has no effect on 8 12 or 16 bpp pixel formats 1 Big endian pixel ordering within a byte 0 Little endian ordering within a byte 9 BEBO Big Endian Byte Ordering to the LCD 1 Big endian ...

Page 127: ...110 Invalid 111 Invalid 0 LCDEN Color LCD Controller Enable LCD displays usually require that their logic signals be operating before the high voltages are applied to the dis play Thus the LCDVDDEN output signal is not asserted unless both the LCDEN and PWR bit fields have been programmed to 1 Most LCD dis plays require that the controller be enabled LCDEN 1 approximately 20 ms before power is app...

Page 128: ...ed Reading returns 0 Write the reset value 4 MBEI AMBA AHB Master Bus Error Status Indicates that the CLCDC AHB master has encountered a bus error response from a slave 1 Interrupt asserted 0 No interrupt 3 VCI Vertical Compare Set to 1 when one of the four vertical regions selected in the CONTROL register is reached 1 Interrupt asserted 0 No interrupt 2 BUI LCD Next Base Address Update Mode depen...

Page 129: ... 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD MBEIM VCIM BUIM FUIM RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFF4000 0x24 Table 4 31 INTERRUPT Fields BIT NAME DESCRIPTION 31 5 Reserved Reading returns 0 Write the reset value 4 MBEIM Masked AHB Master Error Interrupt 1 Interrupt asse...

Page 130: ... 9 8 7 6 5 4 3 2 1 0 FIELD CMBEI CVCI CBUI CFUI RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO WO WO WO WO RO ADDR 0xFFFF4000 0x24 Table 4 33 INTCLR Fields BIT NAME DESCRIPTION 31 5 Reserved Reading returns 0 Write the reset value 4 CMBEI Clear Masked AHB Master Error Interrupt 1 Interrupt cleared 0 No change 3 CVCI Clear Masked Vertical Compare Interrupt 1 Interrupt cle...

Page 131: ...5 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFF4000 0x2C Table 4 35 UPCURR Fields BIT NAME DESCRIPTION 31 0 A31 A0 A31 A0 of the current lower panel data DMA address Values change dynamically Read only Table 4 36 LPCURR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD A31 A30 ...

Page 132: ...LD MB 3 0 MG 3 0 MR 3 0 RESET RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD LB 3 0 LG 3 0 LR 3 0 RESET RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFF4000 0x200 to 0xFFFF4000 0x3FC Table 4 39 PALETTE Fields LH79525 with 12 Bit CLCDC BIT NAME DESCRIPTION 31 Unused Writes have no effect 30 27 MB 3 0 Most Significant Blue palette dat...

Page 133: ...table 25 20 MG 4 0 Most Significant Green Palette Data See the bit 9 5 description in this table 19 16 MR 4 0 Most Significant Red Palette Data See the bit 4 0 description in this table 15 LI Least Significant Intensity Bit Unused for STN displays Can be used as the LSB of the R G and B inputs to a 6 6 6 TFT display effectively doubling the number of available colors from 32 k to 64 k where each c...

Page 134: ...ALI Timing Register 1 0x00C ALITIMING2 ALI Timing Register 2 0x010 0xFFF Reserved Do not access Table 4 43 ALISETUP Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PPL CR RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 RW RO RO RO RW RW RW RW RW RW RW RW...

Page 135: ...G1 Register 1 LCDMOD pin equals the state of MODVAL bit in this register 8 MODVAL Mod Signal Value Specifies the value to force onto the MOD signal 7 5 Reserved Reading returns 0 Write the reset value 4 EN0 LCDVEEEN Output Enable Specifies the general purpose output enable to LCDVEEEN only in Bypass Mode 1 LCDVEEEN signal enabled 0 LCDVEEEN signal disabled 3 DISP Display Control Signal Output Cont...

Page 136: ...the delay number of LCDSPS rising edges to hold LCDMOD LOW before transitioning HIGH MODDEL LCDSPS rising edges 1 11 8 PSCLS LCDPS and LCDCLS Delay Controls the delay in LCDDCLK periods from the first rising edge of the internal CLCDC clock after the leading edge of the internal LCDLP signal not the LCDLP pin no 137 to the leading edge of the LCDREV signal The value of this field must be greater t...

Page 137: ...LS2 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE4000 0x00C Table 4 50 ALITIMING2 Fields BITS NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 9 SPLDEL LCDSPL Delay Controls the delay in LCDDCLK periods of the LCDSPL sig nal during vertical front and back porches This field must be programmed to a value greater than t...

Page 138: ...gnal is controlled by TIMING0 HSW Figure 4 6 also shows that the polarity of the LCDLP signal is set by TIMING2 IHS 4 6 2 STN Vertical Timing Figure 4 7 shows typical vertical timing waveforms for STN panels 4 6 3 TFT Horizontal Timing Figure 4 8 shows typical horizontal timing waveforms for TFT panels 4 6 4 TFT Vertical Timing Figure 4 9 shows typical vertical timing waveforms for TFT panels 4 6 ...

Page 139: ... 4 BIT 8 BIT COLOR OR MONO NOTES 1 The CLCDC clock from the RCPC is scaled within the CLCDC and used to produce the LCDDCLK output CLCDC registers set timing in terms of LCDDCLK pulses to produce the other signals that control an STN display 2 The duration ot the LCDLP signal is controlled by TIMING0 HSW the HSW bit field in the TIMING0 Register 3 The polarity of the LCDLP signal is set by TIMING2...

Page 140: ...ORIZONTAL LINES FRONT PORCH ALL LINES FOR ONE FRAME VSS LCDVDDEN DIGITAL SUPPLY ENABLE FOR HIGH VOLTAGE SUPPLIES LCDDCLK PANEL CLOCK TIMING2 PCD TIMING2 BCD TIMING2 IPC TIMING2 CPL LCDEN DATA ENABLE TIMING2 ACB TIMING2 IOE LCDFP VERTICAL SYNCHRONIZATION PULSE TIMING1 IVS See Note 3 PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME NOTES 1 Signal polarties may vary for some displays 2 See STN...

Page 141: ...DATA TIMING0 HSW TIMING0 HBP 16 TIMING0 PPL 1 D001 D002 D ONE LINE OF LCD DATA DNNN TIMING0 HFP HORIZONTAL BACK PORCH HORIZONTAL FRONT PORCH ENUMERATED IN LCDDCLKS ENUMERATED IN LCDDCLKS LH79525 41 NOTES 1 The CLCDC clock from the RCPC is scaled within the CLCDC and used to produce the LCDDCLK output CLCDC registers set timing in terms of LCDDCLK pulses to produce the other signals that control a ...

Page 142: ...SEE TFT HORIZONTAL TIMING DIAGRAM ENUMERATED IN HORIZONTAL LINES FRONT PORCH ALL LINES FOR ONE FRAME VSS LCDVDDEN DIGITAL SUPPLY ENABLE LCDDCLK PANEL CLOCK TIMING2 PCD TIMING2 BCD TIMING2 IPC LCDEN DATA ENABLE TIMING2 ACB TIMING2 IOE LCDFP VERTICAL SYNCHRONIZATION PULSE TIMING1 IVS PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME NOTES 1 Signal polarties may vary for some displays 2 The use...

Page 143: ...CE LCDLP HORIZONTAL SYNCHRONIZATION PULSE INPUTS TO THE ALI FROM THE CLCDC OUTPUTS FROM THE ALI TO THE PANEL LCDDCLK PANEL CLOCK TIMING2 PCD TIMING2 BCD TIMING2 IPC TIMING2 CPL LCDVD 11 0 LH79525 LCDVD 15 0 LH79524 16 TIMING0 PPL 1 LCDDCLK DELAYED FOR AD TFT HR TFT LCDVD 11 0 LH79525 LCDVD 15 0 LH79524 DELAYED FOR AD TFT HR TFT LCDSPL AD TFT HR TFT START PULSE LEFT LCDLP HORIZONTAL SYNCHRONIZATION...

Page 144: ...gisters to program DMA enable Transfer Size Byte Half word Word Burst Size 1 4 8 or 16 Address Increment Enable Transfer Direction Maximum Count Terminal Count DMA transactions use a 16 word First In First Out FIFO array with pack and unpack logic to handle all input output combinations of byte half word and word transfers In addition there are external DMA Request DREQ and Acknowledge DACK signal...

Page 145: ...ta Each of the four data streams has its own independent set of DMA Registers and address transfer count counters In addition Stream 2 provides a set of external signals for initiating and controlling DMA transfers between external peripherals and memory The signals DREQ and DACK are brought out to external pins that are multiplexed with other functions Note that any peripheral using the external ...

Page 146: ...he DMA waiting for the external request signal in step 1 The software workaround to this is Set up a memory to memory access Let the memory to memory access complete Execute up the peripheral to memory write but without the enable bit set Perform a second write operation with the enable bit set When Stream 3 is used for memory to memory transfers the transfer starts when software sets an enable bi...

Page 147: ... the Interrupt Controller as a combined interrupt See the Vectored Interrupt Controller chapter for more information on interrupts 5 1 4 External DMA Handshake Signal Timing The basic signal timing for external DMA is illustrated in Figure 5 1 Additional timing is available in the Data Sheet DREQ Timing Once asserted DREQ must not transition from LOW to HIGH again until after nDACK has been assert...

Page 148: ...eam 2 Register Base Address STREAM3 0xFFFE10C0 Data Stream 3 Register Base Address MASK 0xFFFE10F0 DMA Interrupt Mask Register CLR 0xFFFE10F4 DMA Interrupt Clear STATUS 0xFFFE10F8 DMA Status Register Table 5 3 DMA Data Stream Register Summary One Set of Registers for Each of the Four Data Streams in Table 5 2 ADDRESS OFFSET FROM STREAM BASE NAME DESCRIPTION 0x000 SOURCELO Source Base Address Regis...

Page 149: ... RW RW RW RW RW RW ADDR DATASTREAM x BASE 0x000 Table 5 5 SOURCELO Fields BITS NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 0 SOURCELO Low Order Source Address This field contains the lower 16 bits of the address for the source of data for the next DMA transfer Table 5 6 SOURCEHI Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 ...

Page 150: ...RW RW RW RW ADDR DATASTREAM x BASE 0x008 Table 5 9 DESTLO Fields BITS NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 0 DESTLO Low Order Destination Address This field contains the lower 16 bits of the address for the destination of data for the next DMA transfer Table 5 10 DESTHI Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 ...

Page 151: ...and sets the terminal count If the maximum count is programmed to 0 the DMA Con troller does not perform any function The maximum terminal count is limited by a 16 bit value 216 1 Table 5 12 MAX Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD M...

Page 152: ... is the source 12 Reserved Reading returns 0 Write the reset value 11 M2M Stream 3 Memory Transfer Selects memory to memory transfer for Stream 3 Ignored for data streams 2 0 1 Stream 3 is configured for memory to memory transfer The DMA Controller disregards any request from UART0TX and transfers data from source to destination as fast as possible until MaxCnt expires 0 Stream 3 is not configured...

Page 153: ...SOINC Current Source Register Increment Enables a Current Source Register increment after each source to DMA data transfer 1 Current Source Register increments as data transfers from a source to the DMA The value increments at the end of the address phase of the AHB transfer 0 Current Source Register remains unchanged holding the same value during the entire DMA transfer 0 ENABLE DMA Controller En...

Page 154: ...he UART0 TX FIFO Watermark If set to 10 the UART0 TX FIFO Watermark must be set to 3 4 or smaller If set to 11 the UART0 TX FIFO Watermark must be set to 1 2 or smaller Table 5 18 Constraints on CTRL Field Values Based on Stream Type STREAM TYPE DESIZE SOBURST SOSIZE DEINC SOINC SSPRX Stream 0 All valid values 00 or 10 00 1 0 SSPTX Stream 1 00 00 or 10 All valid values 0 1 UART0RX Stream 2 All val...

Page 155: ...O RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CURSHI RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR DATASTREAM x BASE 0x018 Table 5 20 CURSHI Fields BITS NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 0 CURSHI Current Source Lower Address This field contains the higher 16 bits of the address for the...

Page 156: ...O RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CURDHI RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR DATASTREAM x BASE 0x020 Table 5 24 CURDHI Fields BITS NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 0 CURDHI Current Destination Upper Address This field contains the upper 16 bits of the...

Page 157: ... to the destination and a DMA transfer is finished Table 5 27 TCNT Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TERM RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR DATASTREAM x BASE 0x028 Table ...

Page 158: ...ns 0 Write the reset value 7 MASKE3 Data Stream 3 Error Interrupt 1 Enables data stream 3 error interrupt 0 Disables data stream 3 error interrupt 6 MASKE2 Data Stream 2 Error Interrupt 1 Enables data stream 2 error interrupt 0 Disables data stream 2 error interrupt 5 MASKE1 Data Stream 1 Error Interrupt 1 Enables data stream 1 error interrupt 0 Disables data stream 1 error interrupt 4 MASKE0 Data...

Page 159: ... DESCRIPTION 31 8 Reserved Reading returns 0 Write the reset value 7 CLEARE3 Clear ErrorInt3 Flag 1 Clears the ERRORINT3 interrupt flag in the Status Register 0 No effect 6 CLEARE2 Clear ErrorInt2 Flag 1 Clears the ERRORINT2 interrupt flag in the Status Register 0 No effect 5 CLEARE1 Clear ErrorInt1 Flag 1 Clears the ERRORINT1 interrupt flag in the Status Register 0 No effect 4 CLEARE0 Clear Error...

Page 160: ...sferring data It is HIGH if a data transfer is in progress The Active flags have the same polarity as the Enable bits in the Data Stream Control Register Table 5 33 STATUS Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD ACTIVE3 ACTIVE2 ACTIVE1 ...

Page 161: ...stream 1 error interrupt 1 Error interrupt asserted 0 Error interrupt not asserted 4 ERRORINT0 Data Stream 0 Error Interrupt Contains the status of the data stream 0 error interrupt 1 Error interrupt asserted 0 Error interrupt not asserted 3 INT3 Data Stream 3 Interrupt Flag 1 Interrupt Flag is active 0 Interrupt Flag is not active 2 INT2 Data Stream 2 Interrupt Flag 1 Interrupt Flag is active 0 I...

Page 162: ...ion of transmitted pause frames 802 Q VLAN tagging with recognition of incoming VLAN and priority tagged frames multiple buffers per receive and transmit frame APB interface AHB bus master DMA interface to external system memory Interrupt generation for receive and transmit completion Statistics counter registers for Remote Monitoring RMON and Management Information Base MIB Automatic pad and CRC ...

Page 163: ... for both the LH79524 and LH79525 and all descriptions in this chapter apply to both devices Following the Theory of Operation section is a programming example Figure 6 1 EMAC Block Diagram CONTROL and STATUS REGISTERS ETHERMDIO ETHERMDC ETHERRX 3 0 ETHERRXER ETHERRXDV ETHERRXCLK ETHERRTX 3 0 ETHERTXER ETHERCOL MII ETHERCRS ETHERTXEN ETHERTXCLK STATUS REGISTERS REGISTER INTERFACE ADDRESS CHECKING ...

Page 164: ... software upon initiatlization Software programs the MAC address es into the Address Specific register s and also must use it to build transmit frames Incoming packets are checked for error and validity in the Receive Block Then the Address Checking Block compares addresses of received packets to the addresses stored in the Specific Address Registers and upon match copies the packet to the receive...

Page 165: ...the Ethernet MAC through the DMA interface All transfers are 32 bit words and may be single accesses or bursts of 2 3 or 4 words transfers for the LH79525 are auto matically parsed into two 16 bit transfers to accommodate its 16 bit data bus Four word bursts are the default data transfer however single accesses or bursts fewer than four words may be used to transfer data at the beginning or the en...

Page 166: ...e must clear this bit before the buffer can be used again WORD 1 31 Global All Ones Broadcast Address Detected 30 Multicast Hash Match 29 Unicast Hash Match 28 External Address Match 27 Reserved Reading returns 0 Write the reset value 26 Specific Address Register 1 Match 25 Specific Address Register 2 Match 24 Specific Address Register 3 Match 23 Specific Address Register 4 Match 22 Type ID Match ...

Page 167: ...s 1KB boundaries As receive buffer manager Write functions are two word bursts the RXBQP register should be pro grammed with the three least significant bits as 0 As each receive buffer is used the receive buffer manager programs the Used bit of the first descriptor word to 1 to indicate that buffer has been used If a receive error is detected the receive buffer currently being written will be rec...

Page 168: ...tus Frames can be transmitted with or without automatic CRC generation If CRC is automatically generated a pad will also be automatically generated to make frames a min imum length of 64 bytes Table 6 2 defines the transmit buffer descriptor list For each sta tus bit 1 TRUE and 0 FALSE Table 6 2 Transmit Buffer Descriptor List BIT FUNCTION WORD 0 31 0 Byte Address Of Buffer WORD 1 31 Used Must be ...

Page 169: ...transmit queue Note that disabling receive does not have the same effect on the receive queue pointer Once the transmit queue is initialized transmit is activated by writing to the NETCTL STARTTX bit Transmit is halted when a buffer descriptor with its Used bit set is read if a transmit error occurs or by writing to the NETCTL TXHALT bit Transmission is suspended if a pause frame is received while...

Page 170: ...programming NETCONFIG DISCARDFCS to 1 This causes the appended bytes to be discarded instead of being copied to memory However the appended bytes are still transmitted with the frame and are filled with 0s When operating with Jumbo Frames be sure to remove the FCS fields from the frame data 6 1 4 Transmit Block The Transmit Block transmits frames in accordance with the Ethernet IEEE 802 3 CSMA CD ...

Page 171: ...gister PAUSETIME is updated with the frame s pause time regardless of its current contents and regardless of the state of the NETCONFIG PAUSEEN bit An interrupt is asserted when a pause frame is received assuming it is enabled in the Interrupt Mask register If NETCONFIG PAUSEEN is 1 and the value of the PAUSETIME register is non zero no new frame is transmitted A valid pause frame has a destinatio...

Page 172: ... using normal frame transmission methods A pause frame can be sent while the transmitter is paused by resetting the NETCONFIG PAUSEEN bit 6 1 5 Address Checking Block The Address Checking Block examines the destination addresses of received frames and indicates to the DMA Block which frames should be copied to memory Whether a frame is copied depends on the Network Configuration register the conte...

Page 173: ...h bit of the destination address HASH_INDEX 5 XOR DA 5 DA 11 DA 17 DA 23 DA 29 DA 35 DA 41 DA 47 HASH_INDEX 4 XOR DA 4 DA 10 DA 16 DA 22 DA 28 DA 34 DA 40 DA 46 HASH_INDEX 3 XOR DA 3 DA 09 DA 15 DA 21 DA 27 DA 33 DA 39 DA 45 HASH_INDEX 2 XOR DA 2 DA 08 DA 14 DA 20 DA 26 DA 32 DA 38 DA 44 HASH_INDEX 1 XOR DA 1 DA 07 DA 13 DA 19 DA 25 DA 31 DA 37 DA 43 HASH_INDEX 0 XOR DA 0 DA 06 DA 12 DA 18 DA 24 D...

Page 174: ...can support frame lengths up to 1 536 bytes 18 bytes more than the original Ethernet maximum frame length of 1 518 bytes This is enabled by programming the NETCONFIG RECBYTE bit to 1 Bits 21 16 of the Receive Buffer Descriptor List see Table 6 1 provide information about VLAN tagged frames Bit 21 1 if the receive frame is VLAN tagged Type ID 0x8100 Bit 20 1 if receive frame is priority tagged Type...

Page 175: ...ory address of Receive Buffer Descriptor List to the RXBQP register 5 The receive circuits can then be enabled by writing to the HASHBOT HASHTOP SPECADxBOT and SPECADxTOP address recognition registers and then program ming NETCTL RXEN to 1 to enable the receive circuit 6 2 1 1 1 Address Matching The HASHBOT HASHTOP and the four SPECADxBOT SPECADxTOP register pairs must be programmed with the appro...

Page 176: ...for handling the data in the buffer and then releasing the buffer by writing the ownership bit back to 0 then clearing the interrupt If the EMAC is unable to write the data at a rate to match the incoming frame a Receive Overrun interrupt is set If there is no receive buffer available i e the next buffer is still owned by software the Receive Buffer Not Available interrupt is set If the frame is n...

Page 177: ...ts can then be enabled by programming NETCTL TXEN to 1 6 2 1 3 Transmitting Frames To set up a frame for transmission 1 Program NETCTL TXEN to 0 2 Allocate an area of system memory for transmit data This does not have to be con tiguous varying lengths can be used as long as they conclude on byte borders 3 Set up the transmit buffer list 4 Program NETCTL TXEN to 1 and enable interrupts by programmi...

Page 178: ...f the management operation the bits will have shifted back to their original locations For a read operation the data bits are updated with data read from the PHY ETHERMDC should not toggle faster than 2 5 MHz ETHERMDC is generated by dividing down HCLK The NETCONFIG DIV bits set the divisor for HCLK to produce ETHERMDC The default is 32 which is acceptable for HCLK running up to 80 MHz 6 2 1 6 Int...

Page 179: ...TUS Network Status Register 0x0C Reserved 0x10 Reserved 0x14 TXSTATUS Transmit Status Register 0x18 RXBQP Receive Buffer Queue Pointer 0x1C TXBQP Transmit Buffer Queue Pointer 0x20 RXSTATUS Receive Status Register 0x24 INSTATUS Interrupt Status Register 0x28 ENABLE Interrupt Enable Register 0x2C DISABLE Interrupt Disable Register 0x30 MASK Interrupt Mask Register 0x34 PHYMAINT PHY Maintenance Regi...

Page 180: ...PAUSEFM Transmitted pause frames MATCHING REGISTERS 0x90 HASHBOT Hash register bottom 31 0 0x94 HASHTOP Hash register top 63 32 0x98 SPECAD1BOT Specific address 1 bottom 0x9C SPECAD1TOP Specific address 1 top 0xA0 SPECAD2BOT Specific address 2 bottom 0xA4 SPECAD2TOP Specific address 2 top 0xA8 SPECAD3BOT Specific address 3 bottom 0xAC SPECAD3TOP Specific address 3 top 0xB0 SPECAD4BOT Specific addr...

Page 181: ...RW RW RW ADDR 0xFFFC7000 0x00 Table 6 7 NETCTL Fields BITS NAME FUNCTION 31 13 Reserved Reading returns 0 Write the reset value 12 TXZEROQ Transmit Zero Quantum Pause Frame Causes a pause frame with zero pause quantum to be transmitted at the next available transmitter idle time 1 Transmit zero quantum pause frame 0 No action 11 TXPFRAME Transmit Pause Frame Transmit a pause frame with the pause q...

Page 182: ...abled transmission stops immediately the transmit FIFO and control registers are cleared and the TXBPQ register is reset to point to the start of the Transmit Descriptor list 1 Enable Ethernet transmitter 0 Disable Ethernet transmitter 2 RXEN Receive Enable Enables the EMAC to receive data When disabled frame reception stops immediately and the receive FIFO is cleared The RXBPQ register is unaffec...

Page 183: ... FCS CRC errors or count FCS errors 0 Normal operation 18 ENFRM Enable Frames Enable frames to be received in half duplex mode while transmitting 1 Enable frame receipt in half duplex mode while transmitting 0 Disable frame receipt in half duplex mode while transmitting 17 DISCARDFCS Discard Receive FCS Specifies whether the FCS field of received frames will be copied to memory 1 Do not copy FCS f...

Page 184: ...MAC to receive multicast frames when the six bit hash function of the destination address points to a bit that is set in the hash register 1 Receive multicast frames when hash function active 0 Normal operation 5 NOBCAST No Broadcast Allows configuration of the EMAC so that frames addressed to a Broadcast address of all 1s will not be received 1 Do not receive frames sent to Broadcast address of a...

Page 185: ...LD PHYIDLE MDIOINSTAT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 1 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFC7000 0x08 Table 6 11 NETSTATUS Fields BITS NAME FUNCTION 31 3 Reserved Reading returns 0 Write the reset value 2 PHYIDLE PHY Logic Idle The PHY management logic is idle i e has completed 1 PHY Management Logic is idle 0 PHY Management Logic is active 1 MDIOINSTAT ETHERMDIO Input ...

Page 186: ...RO RO RO RW RW RW RO RW RW RW ADDR 0xFFFC7000 0x14 Table 6 13 TXSTATUS Fields BITS NAME FUNCTION 31 7 Reserved Reading returns 0 Write the reset value 6 TXUNDER Transmit Underrun This bit shows when transmit DMA was not able to read data from the buffer in system memory The cause can be that the AHB or ASB bus was not granted in time a Not OK response was returned a zero length buffer was read or ...

Page 187: ...Transmit is not active Write 1 Reset bit to 0 0 No effect 2 RETRYLIMIT Retry Limit Exceeded Indicates that the transmission retry limit was exceeded Read 1 Retry limit exceeded 0 Normal operation Write 1 Reset bit to 0 0 No effect 1 COLLISION Collision Occurred Indicates that a collision occurred Read 1 Collision occurred 0 Normal operation Write 1 Reset bit to 0 0 No effect 0 USEDBIT Used Bit Rea...

Page 188: ...should instead work its way through the buffer descriptor queue checking the used bits Receive buffer writes also comprise bursts of two words and as with transmit buffer reads it is recommended that bit 2 is always written with zero to prevent a burst from crossing a 1KB boundary in violation of Section 3 6 of the AMBA specification Table 6 14 RXBQP Register BIT 31 30 29 28 27 26 25 24 23 22 21 2...

Page 189: ...s it is recommended that bit 2 is always written with zero This is to prevent a burst from crossing a 1KB boundary in vio lation of Section 3 6 of the AMBA specification Table 6 16 TXBQP Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD TXBQP RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD T...

Page 190: ...RXCOVERRUN Receive Overrun The DMA Block was unable to store the receive frame to memory Either because the AHB bus was not granted in time or because a Not OK response was returned The buffer will be recovered if this happens Read 1 DMA unable to store receive frame 0 Normal operation Write 1 Reset bit to 0 0 No effect 1 FRMREC Frame Received Indicates that one or more frames have been received a...

Page 191: ...TXUSDBITRD RXUSDBITRD RXCOMP MNGFRMSENT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RW RW RW RW RW RO RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0x24 Table 6 21 INSTATUS Fields BITS NAME FUNCTION 31 14 Reserved Reading returns 0 Write the reset value 13 PAUSEZERO Pause Time Zero Indicates the PAUSETIME register has decre mented to zero This bit is reset to 0 when read 1 PAUSETIME decremented to zero ...

Page 192: ... time for it to be transmitted or response returned Not OK Also 1 if a Used bit is read mid frame or when a new Transmit Queue Pointer is written This bit is reset to 0 when read 1 Transmit buffer underrun 0 No error 3 TXUSDBITRD Transmit Used Bit Read Indicates that a transmit buffer descriptor has been read with its Used bit set This bit is reset to 0 when read 1 Used bit set 0 No error 2 RXUSDB...

Page 193: ...O WO WO WO WO WO WO WO WO WO WO WO WO WO ADDR 0xFFFC7000 0x28 Table 6 23 ENABLE Fields BITS NAME FUNCTION 31 14 Reserved Reading returns 0 Write the reset value 13 PAUSETMZEROIEN Pause Time Zero Interrupt Enable 12 PAUSEFRRXIEN Pause Frame Received Interrupt Enable 11 NOTOKIEN Response Not OK Interrupt Enable 10 RECOVERRUNIEN Receive Overrun Interrupt Enable 9 8 Reserved Reading returns 0 Write th...

Page 194: ...NEIDIS RESET 0 0 TYPE RO RO WO WO WO WO WO WO WO WO WO WO WO WO WO WO ADDR 0xFFFC7000 0x2C Table 6 25 DISABLE Fields BITS NAME FUNCTION 31 14 Reserved Reading returns 0 Write the reset value 13 PAUSETMZEROIDIS Disable Pause Time Zero Interrupt 12 PAUSEFRRXIDIS Disable Pause Frame Received Interrupt 11 NOTOKIDIS Disable Response Not OK Interrupt 10 RECOVERRUNIDIS Disable Receive Overrun Interrupt 9...

Page 195: ...RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFC7000 0x30 Table 6 27 MASK Fields BITS NAME FUNCTION 31 14 Reserved Reading returns 0 Write the reset value 13 PAUSETMZEROMSK 1 Pause Time Zero Interrupt masked 0 Unmasked 12 PAUSEFRRXMSK 1 Pause Frame Received Interrupt masked 0 Unmasked 11 NOTOKMSK 1 Response Not OK Interrupt masked 0 Unmasked 10 RECOVERRUNMSK 1 Receive Overrun Interrupt masked 0 Unmasked ...

Page 196: ...t register At the end of management operation the bits will have shifted back to their original locations For a read operation the data bits will be updated with data read from the PHY Table 6 28 PHYMAINT Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD STARTFRM OPERATION PHYADDR REGADDR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW BI...

Page 197: ...T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFC7000 0x38 Table 6 31 PAUSETIME Fields BITS NAME FUNCTION 31 16 Reserved Reading returns 0 Write the reset value 15 0 PAUSETIME Pause Time Stores the current PAUSETIME value which is decremented every 512 bit times Table 6 32 TXPAUSEQUAN Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIEL...

Page 198: ... 3 1 Pause Frames Received PAUSEFRRX This register allows software to read the number of good pause frames received A good frame has a length of 64 to 1 518 1 522 if NETCONFIG RECBYTE is 1 and has no FCS alignment or receive symbol errors Table 6 34 PAUSEFRRX Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO ...

Page 199: ...IELD FRMTXOK RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0x40 Table 6 37 FRMTXOK Fields BITS NAME FUNCTION 31 24 Reserved Reading returns 0 Write the reset value 23 0 FRMTXOK Frames Transmitted OK Shows the number of successfully transmitted frames Table 6 38 SINGLECOL Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD ...

Page 200: ...RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD MULTFRM RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0x48 Table 6 41 MULTFRM Fields BITS NAME FUNCTION 31 16 Reserved Reading returns 0 Write the reset value 15 0 MULTFRM Multiple Collision Frames Contains the number of successfully transmitted frames that experienced between two and...

Page 201: ... RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD FRCHK RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0x50 Table 6 45 FRCHK Fields BITS NAME FUNCTION 31 8 Reserved Reading returns 0 Write the reset value 7 0 FRCHK Frame Check Sequence Errors Number of Frame Check Sequence errors Table 6 46 A...

Page 202: ... 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD DEFTXFRM RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0x58 Table 6 49 DEFTXFRM Fields BITS NAME FUNCTION 31 16 Reserved Reading returns 0 Write the reset value 15 0 DEFTXFRM Deferred Transmission Frames Deferred transm...

Page 203: ... RW RW RW RW RW RW RW ADDR 0xFFFC7000 0x60 Table 6 53 EXCCOL Fields BITS NAME FUNCTION 31 8 Reserved Reading returns 0 Write the reset value 7 0 EXCCOL Excessive Collisions Number of frames that were not transmitted because they experienced 16 collisions Table 6 54 TXUNDER Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO R...

Page 204: ... 0 TYPE RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0x68 Table 6 57 SENSERR Fields BITS NAME FUNCTION 31 8 Reserved Reading returns 0 Write the reset value 7 0 SENSERR Carrier Sense Errors Number of frames transmitted where carrier sense was not detected during transmission or where carrier sense was deassert ed after being asserted in a transmit frame without a collision no un...

Page 205: ...RW RW RW ADDR 0xFFFC7000 0x6C Table 6 59 RXRERR Fields BITS NAME FUNCTION 31 16 Reserved Reading returns 0 Write the reset value 15 0 RXRERR Receive Resource Errors The number of frames that were address matched but could not be copied to memory because no receive buffer was available Table 6 60 RXOVERR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 ...

Page 206: ... 7 6 5 4 3 2 1 0 FIELD RXSYMERR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0x74 Table 6 63 RXSYMERR Fields BITS NAME FUNCTION 31 8 Reserved Reading returns 0 Write the reset value 7 0 RXSYMERR Receive Symbol Errors Counts the number of frames that had ETHERRXER asserted during reception Table 6 64 LENERR Register BIT 31 30 29 28 27 26...

Page 207: ... RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RXJAB RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0x7C Table 6 67 RXJAB Fields BITS NAME FUNCTION 31 8 Reserved Reading returns 0 Write the reset value 7 0 RXJAB Receive Jabbers Number of receive jabbers Table 6 68 UNDERFRM Register BIT 31 30 29 ...

Page 208: ... RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD SQERR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0x84 Table 6 71 SQERR Fields BITS NAME FUNCTION 31 8 Reserved Reading returns 0 Write the reset value 7 0 SQERR SQE Test Errors Shows the number of frames where the ETHERCOL pin was not asserted within 96 bit...

Page 209: ...8 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TXPAUSEFM RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0x8C Table 6 75 TXPAUSEFM Fields BITS NAME FUNCTION 31 16 Reserved Reading returns 0 Write the reset value 15 0 TXPAUSEFM Transmit...

Page 210: ... 18 17 16 FIELD HASHBOT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD HASHBOT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0x90 Table 6 77 HASHBOT Fields BITS NAME FUNCTION 31 0 HASHBOT Hash Register Bottom Bits 31 0 of the Hash Address Register...

Page 211: ... BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD SPECAD1BOT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0x98 Table 6 81 SPECAD1BOT Fields BITS NAME FUNCTION 31 0 SPECAD1BOT Least Significant Destination Address Bits Least significant bits of the destination address Table 6 82 SPECAD1TOP Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 ...

Page 212: ...1 10 9 8 7 6 5 4 3 2 1 0 FIELD SPECAD2BOT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0xA0 Table 6 85 SPECAD2BOT Fields BITS NAME FUNCTION 31 0 SPECAD2BOT Least Significant Destination Address Bits Least significant bits of the destination address Table 6 86 SPECAD2TOP Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD ...

Page 213: ...1 10 9 8 7 6 5 4 3 2 1 0 FIELD SPECAD3BOT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0xA8 Table 6 89 SPECAD3BOT Fields BITS NAME FUNCTION 31 0 SPECAD3BOT Least Significant Destination Address Bits Least significant bits of the destination address Table 6 90 SPECAD3TOP Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD ...

Page 214: ... 6 5 4 3 2 1 0 FIELD SPECAD4BOT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0xB0 Table 6 93 SPECAD4BOT Fields BITS NAME FUNCTION 31 0 SPECAD4BOT Least Significant Destination Address Bits Least significant bits of the destination address Table 6 94 SPECAD4TOP Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 ...

Page 215: ... 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD IDCHK RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC7000 0xB8 Table 6 97 TypeIDCheck Fields BITS NAME FUNCTION 31 16 Reserved Reading returns 0 Write the reset value 15 0 IDCHK Typ...

Page 216: ... Wait states may be extended indefinitely using the nWAIT pin Two Chip Selects for synchronous and up to four Chip Selects for static memory devices Up to four memory Byte Lane Selects for static memory devices Boot in 8 16 or 32 bit mode 7 1 Theory of Operation The combined dynamic and static memory controller controls all static and dynamic mem ory accesses Figure 7 1 is a block diagram of the E...

Page 217: ...ith 32 bit memory pin A0 carries the A2 address signal and pin A23 carries the A25 address signal This is a bit dif ferent than many memory interfaces but offers advantages such as a greater addressing space for 16 and 32 bit memory systems During an SDRAM memory cycle the bank being accessed is selected by the assertion of the appropriate Chip Select signal This is found by decoding address bit 2...

Page 218: ...n the external memory bus depending on the size of memory devices being addressed For 8 bit memory systems address signal A0 is connected to address pin A0 With a 16 bit system addressing does not require address signal A0 since accesses begin on half word boundaries For 32 bit systems both address signal A0 and A1 are not needed because memory accesses begin on word boundaries Byte Lane Enables s...

Page 219: ...Figure 7 2 Automatic Address Shifting LH79525 114 00 A0 A0 A1 A2 A23 A1 A2 INTERNAL TO THE LH79524 LH79525 EXTERNAL TO THE LH79524 LH79525 A1 A2 A3 A2 A3 A4 A23 A24 A25 01 10 00 01 10 00 01 10 00 01 10 NOTE MEMORY WIDTH SCONFIGx MW 00 8 BIT 01 16 BIT 10 32 BIT MEMORY WIDTH ...

Page 220: ...d from 16 or 32 bit memory devices it is important that the Byte Lane Select BLS bit is set to 1 within the respective memory bank control reg ister This asserts all nBLEx lines LOW during a read access as during a read all bytes of the device must be selected to avoid un driven byte lanes on the read data value In the case of 16 and 32 bit wide memory devices byte select signals exist and these m...

Page 221: ...t Devices Figure 7 5 8 bit Memory Bank nCE nOE nWE IO 7 0 nBLE3 nCS A 20 0 nOE D 31 24 LH79525 82 nCE nOE nWE IO 7 0 nBLE2 D 23 16 nCE nOE nWE IO 7 0 nBLE1 D 15 8 nCE A 20 0 A 20 0 A 20 0 A 20 0 nOE nWE IO 7 0 nBLE0 D 7 0 LH79525 83 A 20 0 nCE nOE A 20 0 nCE nOE nWE IO 7 0 nBLE1 D 15 8 A 20 0 nCE nOE nWE IO 7 0 nBLE0 D 7 0 LH79525 84 A 20 0 nCE nOE nWE D 7 0 A 20 0 nCE nOE nWE IO 7 0 ...

Page 222: ... bit Memory Bank Constructed From a Single 32 bit Device nCS A 20 0 nOE nWE LH79525 85 nCE nOE nWE nUB nLB IO 15 0 nBLE2 nBLE3 D 31 16 nCE A 20 0 A 20 0 nOE nWE nUB nLB IO 15 0 nBLE0 nBLE1 D 15 0 nCE A 20 0 nOE nWE nUB nLB IO 15 0 nCS A 20 0 nOE nWE nBLE1 nBLE0 D 15 0 LH79525 86 nCE A 20 0 nOE nWE nB3 nB2 nB1 nCS A 20 0 nOE nWE nBLE3 nBLE2 nBLE1 nB0 nBLE0 IO 31 0 D 31 0 ...

Page 223: ...T MASK ROM 64K 16 SRAM 2 128K 8 SRAM 4 IO 15 0 A 20 0 nCS0 nOE nCS1 nWE nCS2 nBLE3 nBLE2 nBLE1 nBLE0 nOE nWE nUB nLB nCE A 20 0 Q 31 0 D 31 0 D 31 16 D 31 24 D 23 16 D 15 8 D 7 0 D 15 0 nOE nCE A 15 0 IO 15 0 nOE nWE nUB nLB nCE A 16 0 IO 7 0 nOE nWE nCE A 16 0 IO 7 0 nOE nWE nCE A 16 0 IO 7 0 nOE nWE nCE A 16 0 IO 7 0 nOE nWE LH79525 93 ...

Page 224: ... 3 1 Simple Shifting Subroutine If the application requires specific signals on specific address lines it may be necessary to pre shift the address before executing a Read or Write When addressing 16 or 32 bit wide devices a subroutine based on the flow chart in Figure 7 9 handles the necessary pre shifting Device Width can be determined by reading the SCONFIGx MW field Figure 7 9 Pre shifting Rou...

Page 225: ...ers allow programming wait states and the SWAITWENx and SWAITOENx register allow delaying assertion of the nWE nBLEx nOE signals The BTC field in the Bank Control Register sets the number of bus turnaround wait states added between external read and write transfers For ease in describing the memory timing letters are used in the following diagrams to represent the values programmed into the above ...

Page 226: ...ng the data into the SoC The address line is held valid one more HCLK period denoted by C in the diagram Wait states are programmed using the SWAITRDx register Figure 7 11 shows the results of programming SWAITRDx E to 0x3 creating three wait states In the Figure Timing A illustrates programming SWAITOENx to 0x0 and SWAITRDx to 0x3 With no wait states the date would be read on the rising edge of n...

Page 227: ... is one represented by time D1 Then instead of the nOE signal deasserting one HCLK period later it is extended two wait states because of the programmed value in SWAITRDx The result is the same delay of three HCLK periods but achieved in a different way to also delay assertion of nOE Figure 7 11 Static Read Transaction with Three Wait States HCLK A 23 0 VALID DATA VALID ADDRESS LH79525 110 D 31 0 ...

Page 228: ...n be programmed using the appropriate mix of nOE extension programmed in SWAITRDx with nOE assertion delay programmed in SWAITOENx 7 2 4 1 2 Write Cycle Wait States Write timing starts with assertion of the appropriate memory bank chip selects nCSx and address signals A 23 0 The write access time is determined by the number of wait states programmed in the SWAITWRx register Figure 7 12 shows the m...

Page 229: ...Select Wait states behave slightly differently for Write transactions than for Reads Instead of the length of the Write cycle tWC being the sum of the value programmed into the SWAITWENx and SWAITWRx registers it has the following relationship tWC tA0 tB0 tB1 tBn C where the length of each term is one HCLK period and n is the value programmed in the respective register The minimum value for the eq...

Page 230: ...he conclusion of A2 and deasserts at the con clusion of B2 Obviously if SWAITWENx SWAITWRx no nWE nBLEx would exist As with Reads multiple register values produce the same number of wait states For Write transactions only the contents of SWAITWRx specify the number of wait states Figure 7 13 Static Write Transaction with Two Wait States HCLK A 23 0 VALID ADDRESS LH79525 112 NOTES With Register Pro...

Page 231: ...ponse to be generated Each memory Chip Select space can be 8 16 or 32 bits wide The type of memory used determines how the nWE and nBLEx signals are connected to provide byte half word and word access For read accesses the nBLEx signals must be either all HIGH or all LOW This is done by programming the Byte Lane State BLS bit in the SCONFIG register SCONFIG BLS 7 2 4 4 Write Protection Each static...

Page 232: ... Flash Read Enable nFRE signals When used for booting the NAND Flash must be selected with Chip Select nCS0 which has been programmed as GPIO PM0 If not used for booting the NAND Flash device can be selected with any Chip Select signal See Chapter 3 and the examples that follow for more information about the Boot Controller 7 3 1 Booting Example Booting from NAND Flash is defined by the static sig...

Page 233: ...C NAND Flash Small Block 16 bit 4 byte Address 0xD NAND Flash Small Block 16 bit 5 byte Address 0xE RESERVED Reserved Reserved 0xF RESERVED Reserved Reserved Table 7 3 Boot Configuration for Silicon Version A 1 PC 7 4 DEVICE TYPE DATA BUS WIDTH CONTROL 0x0 NOR Flash or SRAM 16 bit nBLEx LOW for Reads 0x1 NOR Flash or SRAM 16 bit nBLEx HIGH for Reads 0x2 NOR Flash or SRAM 8 bit nBLEx LOW for Reads ...

Page 234: ...External Memory Controller Version 1 0 7 19 Figure 7 14 Connection to NAND Flash LH79525 115 nCS0 nCE A3 A4 A22 A23 DATA ADDRESS COMMAND ALE CLE nWE nRE ALE LH79524 LH79525 NAND FLASH CLE nFWE nFRE D 15 0 or D 7 0 IO 15 0 or IO 7 0 ...

Page 235: ...e any address lines or GPIO to control the device Since NAND Flash devices are available in several widths it is up to software to ensure that the proper control signals appear on the proper address pins for correct operation Recall from Section 7 2 2 1 3 that the SoC right justifies addressing For example using pins D 15 0 to communicate with the NAND Flash requires program ming SCONFIGx MW to 0b...

Page 236: ...a write to location 0x4XXX10 causes nFWE to go LOW C Writing to location 0xCXX10 again drives nFWE HIGH which latches the address in the NAND Flash D Finally to clear the interface write to address 0xCXXX00 forcing ALE to LOW E 7 3 2 3 Address Examples If nCS0 is used to connect 8 bit NAND Flash use the following addresses 0x40800000 to read from NAND Flash 0x40800008 to write address to NAND Flas...

Page 237: ... a word generates an error response 7 4 3 Bus Address Mapping These tables provide the mapping of AHB address bus addresses to the external dynamic memory address for various memory configurations and bus widths The address mapping is selected by programming the Address Mapping AM bits in the DYNCFGx register Note that Auto Precharge is always presented on A10 column address Table 7 5 32 bit Wide ...

Page 238: ...lumn Address 11 BA1 10 BA0 AP 9 8 7 6 5 4 3 2 32 BIT DEVICE 256M SDRAM 16M 16 RBC External Address Pin A 14 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AHB Address To Row Address 11 BA1 12 BA0 25 24 23 22 21 20 19 18 17 16 15 14 13 AHB Address To Column Address 11 BA1 12 BA0 AP 10 9 8 7 6 5 4 3 2 32 BIT DEVICE 256M SDRAM 32M 8 RBC External Address Pin A 14 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AHB Address...

Page 239: ...ternal Address Pin A 14 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AHB Address To Row Address 25 BA1 24 BA0 23 22 21 20 19 18 17 16 15 14 13 12 AHB Address To Column Address 25 BA1 24 BA0 AP 11 10 9 8 7 6 5 4 3 2 32 BIT DEVICE 256M SDRAM 8M 32 BRC External Address Pin A 14 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AHB Address To Row Address 23 BA1 24 BA0 22 21 20 19 18 17 16 15 14 13 12 11 10 AHB Address To ...

Page 240: ... 4 3 2 16 BIT WIDE DEVICE 128M SDRAM 8M 16 RBC External Address Pin A 14 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AHB Address To Row Address 11 BA1 10 BA0 23 22 21 20 19 18 17 16 15 14 13 12 AHB Address To Column Address 11 BA1 10 BA0 AP 9 8 7 6 5 4 3 2 16 BIT WIDE DEVICE 128M SDRAM 16M 8 RBC External Address Pin A 14 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AHB Address To Row Address 11 BA1 12 BA0 24 23 ...

Page 241: ...3 2 16 BIT WIDE DEVICE 128M SDRAM 8M 16 BRC External Address Pin A 14 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AHB Address To Row Address 23 BA1 22 BA0 21 20 19 18 17 16 15 14 13 12 11 10 AHB Address To Column Address 23 BA1 22 BA0 AP 9 8 7 6 5 4 3 2 16 BIT WIDE DEVICE 128M SDRAM 16M 8 BRC External Address Pin A 14 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AHB Address To Row Address 23 BA1 24 BA0 22 21 20 ...

Page 242: ... on write cycles to disable bytes unaffected by the transfer For 16 bit wide memory systems DQM 1 is used as the memory system upper data mask UDQM and DQM 0 is used as the lower data mask LDQM For 32 bit transfers in 16 bit wide memory systems two memory data phases are required to complete the memory cycles Half word 16 bit and byte width transfers complete in one data phase Table 7 9 Memory Sys...

Page 243: ...elf Refresh Exit Time 0x03C DOACTIVE Dynamic Memory Last Data Out to Active Time 0x040 DIACTIVE Dynamic Memory Data In to Active Command Time 0x044 DWRT Dynamic Memory Write Recovery Time 0x048 DYNACTCMD Dynamic Memory Active to Active Command Period 0x04C DYNAUTO Dynamic Memory Auto Refresh Period and Auto Refresh to Active Command Period 0x050 DYNREFEXIT Dynamic Memory Exit Self Refresh to Activ...

Page 244: ...y Write Delay for nCS1 0x238 STURN1 Static Memory Turn Around Delay for nCS1 0x23C Reserved 0x240 SCONFIG2 Static Memory Configuration for nCS2 0x244 SWAITWEN2 Static Memory Write Enable Delay for nCS2 0x248 SWAITOEN2 Static Memory Output Enable Delay for nCS2 0x24C SWAITRD2 Static Memory Read Delay for nCS2 0x250 SWAITPAGE2 Static Memory Page Mode Read Delay for nCS2 0x254 SWAITWR2 Static Memory ...

Page 245: ...UNCTION 31 3 Reserved Reading returns 0 Write the reset value 2 MODE Mode select Entering low power mode reduces memory controller power consumption Dynamic memory is refreshed as necessary The memory con troller returns to normal functional mode by clearing the low power mode bit External memory cannot be accessed in low power state If a memory access is performed an error response is generated 1...

Page 246: ... 0x004 Table 7 14 STATUS Fields BITS NAME FUNCTION 31 3 Reserved Reading returns 0 Write the reset value 2 SA Self refresh Acknowledge This bit indicates the operating mode of the EMC 1 Self refresh Mode 0 Normal Mode 1 WRBUF Write Buffer Status This enables the EMC to enter low power mode or dis abled mode cleanly by determining if the write buffers contain data or not 1 Write Buffers contain dat...

Page 247: ...owed ensuring that changing parameters will not corrupt external data Low Power Mode automatically refreshes SDRAM Disable Mode requires commanding the SDRAM to Self Refresh DYNMC TRL SR 1 prior to entering Disable Table 7 15 CONFIG Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14...

Page 248: ...rved Reading returns 0 Write the reset value 5 MEMCC Memory Clock Control Disabling SDCLK can be performed if there are no SDRAM memory transactions When enabled this field can be used in conjunction with the dynamic memory clock control CS field 1 SDCLK disabled 0 SDCLK enabled 4 3 Reserved Reading returns 0 Write the reset value 2 SR Self Refresh Request Software can command the EMC into self re...

Page 249: ...ever these control bits can if necessary be altered during normal operation Writing a value of 0x000 disables refreshing Programming any other value n results in a delay between refresh cycles of 16 n For example for the refresh period of 16 µs and an HCLK frequency of 50 MHz the following value must be programmed into this register 16 10 6 50 106 16 50 or 0x032 Table 7 19 DYNMREF Register BIT 31 ...

Page 250: ... initialization if the SDRAM controller is used Table 7 21 DYNMRCON Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RDS RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW ADDR 0xFFFF1000 0x028 Table 7 2...

Page 251: ...NABLE 0 When in these two modes external memory access is not allowed ensuring that changing parameters will not corrupt external data Low Power Mode automatically refreshes SDRAM Disable Mode requires commanding the SDRAM to Self Refresh DYNMCTRL SR 1 prior to entering Disable Table 7 23 PRECHARGE Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 252: ...sable Mode CONTROL ENABLE 0 When in these two modes external memory access is not allowed ensuring that changing parameters will not corrupt external data Low Power Mode automatically refreshes SDRAM Disable Mode requires commanding the SDRAM to Self Refresh DYNMC TRL SR 1 prior to entering Disable Table 7 25 DYNM2PRE Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0...

Page 253: ...ory controller is idle then entering Low Power Mode CONTROL MODE 1 or Disable Mode CONTROL ENABLE 0 When in these two modes external memory access is not allowed ensuring that changing parameters will not corrupt external data Low Power Mode automatically refreshes SDRAM Disable Mode requires commanding the SDRAM to Self Refresh DYNMC TRL SR 1 prior to entering Disable Table 7 27 REFEXIT Register ...

Page 254: ...Mode CONTROL ENABLE 0 When in these two modes external memory access is not allowed ensuring that changing parameters will not corrupt external data Low Power Mode automatically refreshes SDRAM Disable Mode requires commanding the SDRAM to Self Refresh DYNMCTRL SR 1 prior to entering Disable Table 7 29 DOACTIVE Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 ...

Page 255: ...ode CONTROL ENABLE 0 When in these two modes external memory access is not allowed ensuring that changing parameters will not corrupt external data Low Power Mode automatically refreshes SDRAM Disable Mode requires commanding the SDRAM to Self Refresh DYNMCTRL SR 1 prior to entering Disable Table 7 31 DIACTIVE Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0...

Page 256: ...CONTROL ENABLE 0 When in these two modes external memory access is not allowed ensuring that changing parameters will not corrupt external data Low Power Mode automatically refreshes SDRAM Disable Mode requires commanding the SDRAM to Self Refresh DYNMCTRL SR 1 prior to entering Disable Table 7 33 DWRT Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0...

Page 257: ...he memory controller is idle then entering Low Power Mode CONTROL MODE 1 or Disable Mode CONTROL ENABLE 0 When in these two modes external memory access is not allowed ensuring that changing parameters will not corrupt external data Low Power Mode automatically refreshes SDRAM Disable Mode requires commanding the SDRAM to Self Refresh DYNMCTRL SR 1 prior to entering Disable Table 7 35 DYNACTCMD Re...

Page 258: ...ng Low Power Mode CONTROL MODE 1 or Disable Mode CONTROL ENABLE 0 When in these two modes external memory access is not allowed ensuring that changing parameters will not corrupt external data Low Power Mode automatically refreshes SDRAM Disable Mode requires commanding the SDRAM to Self Refresh DYNMCTRL SR 1 prior to entering Disable Table 7 37 DYNAUTO Register BIT 31 30 29 28 27 26 25 24 23 22 2...

Page 259: ...sable Mode CONTROL ENABLE 0 When in these two modes external memory access is not allowed ensuring that changing parameters will not corrupt external data Low Power Mode automatically refreshes SDRAM Disable Mode requires commanding the SDRAM to Self Refresh DYNMCTRL SR 1 prior to entering Disable Table 7 39 DYNREFEXIT Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 ...

Page 260: ...Mode CONTROL ENABLE 0 When in these two modes external memory access is not allowed ensuring that changing parameters will not corrupt external data Low Power Mode automatically refreshes SDRAM Disable Mode requires commanding the SDRAM to Self Refresh DYNMCTRL SR 1 prior to entering Disable Table 7 41 DYNACTIVEAB Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0...

Page 261: ... or Disable Mode CONTROL ENABLE 0 When in these two modes external memory access is not allowed ensuring that changing parameters will not corrupt external data Low Power Mode automatically refreshes SDRAM Disable Mode requires commanding the SDRAM to Self Refresh DYNMCTRL SR 1 prior to entering Disable Table 7 43 DYNAMICTMRD Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET...

Page 262: ...de CONTROL ENABLE 0 When in these two modes external memory access is not allowed ensuring that changing parameters will not corrupt external data Low Power Mode automatically refreshes SDRAM Disable Mode requires commanding the SDRAM to Self Refresh DYNMCTRL SR 1 prior to entering Disable However if necessary these control bits can be altered during normal operation Table 7 45 WAIT Register BIT 3...

Page 263: ...eset value 20 P Write Protect 1 Write protected 0 Not Write protected 19 B Read and Write Buffer Enable The Buffer Enable bit must be set to 1 for prop er SDRAM interface operation The buffers must be disabled during SDRAM and SyncFlash initialization They must also be disabled when performing SyncFlash commands The buffers must be enabled during normal operation NOTE The buffers must be disabled ...

Page 264: ...Mb 4M 16 4 banks row length 12 column length 8 0 1 010 00 128Mb 16M 8 4 banks row length 12 column length 10 0 1 010 01 128Mb 8M 16 4 banks row length 12 column length 9 0 1 011 00 256Mb 32M 8 4 banks row length 13 column length 10 0 1 011 01 256Mb 16M 16 4 banks row length 13 column length 9 0 1 100 00 512Mb 64M 8 4 banks row length 13 column length 11 0 1 100 01 512Mb 32M 16 4 banks row length 1...

Page 265: ...st of 8 when configured to access 16 bit memory devices Similarly it does burst of 4 when configured to access 32 bit memory devices 32 BIT EXTERNAL BUS LOW POWER SDRAM ADDRESS MAPPING ROW BANK COLUMN 1 1 000 00 16Mb 2M 8 2 banks row length 11 column length 9 1 1 000 01 16Mb 1M 16 2 banks row length 11 column length 8 1 1 001 00 64Mb 8M 8 4 banks row length 12 column length 9 1 1 001 01 64Mb 4M 16...

Page 266: ...ernal data Low Power Mode automatically refreshes SDRAM Disable Mode requires commanding the SDRAM to Self Refresh DYNMCTRL SR 1 prior to entering Disable NOTE The RAS to CAS latency RAS and CAS latency CAS are both defined in HCLK clock cycles Table 7 50 DYNRASCASx Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO...

Page 267: ...E0 isn t driven externally at reset reset value will be 0 Other chip selects always have a reset value of 0 2 The reset value for nCS1 changes accordingly to what boot mode width is selected If nBLE2 and nBLE1 aren t driven externally at reset system will boot in 16 bit mode with MW resetting to 0b01 Other chip selects always have a reset value of 0b00 Table 7 52 SCONFIGx Register BIT 31 30 29 28 ...

Page 268: ...hat the bus is driven In this case the BLS bit must be HIGH IMPORTANT When accessing NAND Flash this bit must be programmed to 1 by the Boot ROM code for proper operation Writes 1 The active bits in nBLE 3 0 are LOW 0 The active bits in nBLE 3 0 are HIGH Reads 1 The active bits in nBLE 3 0 are LOW 0 All the bits in nBLE 3 0 are HIGH 6 PC Chip Select Polarity 1 active HIGH Chip Select 0 active LOW ...

Page 269: ...ring system initialization or when there are no current or outstanding transactions Software can ensure that there are no current or outstanding transactions by waiting until the memory controller is idle then entering Low Power Mode CONTROL MODE 1 or Disable Mode CONTROL ENABLE 0 When in these two modes external memory access is not allowed ensuring that changing parameters will not corrupt exter...

Page 270: ...These registers must only be modified during system initialization or when there are no current or outstanding transactions Software can ensure that there are no current or outstanding transactions by waiting until the memory controller is idle then entering Low Power Mode CONTROL MODE 1 or Disable Mode CONTROL ENABLE 0 When in these two modes external memory access is not allowed ensuring that ch...

Page 271: ...ly be modified during system initialization or when there are no current or outstanding transactions Software can ensure that there are no current or out standing transactions by waiting until the memory controller is idle then entering Low Power Mode CONTROL MODE 1 or Disable Mode CONTROL ENABLE 0 When in these two modes external memory access is not allowed ensuring that changing parameters will...

Page 272: ...external data Low Power Mode automatically refreshes SDRAM Disable Mode requires commanding the SDRAM to Self Refresh DYNMCTRL SR 1 prior to entering Disable Table 7 60 SWAITPAGEx Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD WAITPAGE RESET...

Page 273: ...em initialization or when there are no current or outstanding transactions Software can ensure that there are no current or outstanding transactions by waiting until the memory controller is idle then entering Low Power Mode CONTROL MODE 1 or Disable Mode CONTROL ENABLE 0 When in these two modes external memory access is not allowed ensuring that changing parameters will not corrupt external data ...

Page 274: ...h DYNMCTRL SR 1 prior to entering Disable To prevent bus contention on the external memory data bus the BTC field controls the number of bus turnaround cycles added between static memory read and write accesses The BTC field also controls the number of turnaround cycles between static memory and dynamic memory accesses Table 7 64 STURNx Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 275: ... configured as GPIO at reset 8 1 1 Port Configuration Port pins can be configured individually as inputs or outputs except of course Ports J and M The direction of each pin is programmed using the Data Direction Registers P1DDRx and P2DDRx Data for output pins is written to the port Data Register P1DRx and P2DRx Input data is read from the same registers Table 8 1 GPIO Ports PORT LH79524 GPIO LH79...

Page 276: ...xed Function column Table 8 2 LH79524 GPIO Multiplexing CABGA NO AT RESET MULTIPLEXED FUNCTION S N1 PA0 INT2 UARTRX2 UARTIRRX2 M2 PA1 INT3 UARTTX2 UARTIRTX2 L3 PA2 CTCAP0A CTCMP0A M1 PA3 CTCAP0B CTCMP0B L2 PA4 CTCAP1A CTCMP1A L1 PA5 CTCAP1B CTCMP1B K3 PA6 CTCAP2A CTCMP2A SDA K2 PA7 CTCAP2B CTCMP2B SCL R2 PB0 nDACK nUARTCTS0 R1 PB1 DREQ nUARTRTS0 P2 PB2 SSPFRM I2SWS N3 PB3 SSPCLK I2SCLK M4 PB4 SSPR...

Page 277: ...11 PF6 LCDEN LCDSPL A12 PF7 LCDFP LCDSPS A5 PG0 ETHERTXEN B6 PG1 ETHERTXCLK A6 PG2 LCDVD0 C7 PG3 LCDVD1 B7 PG4 LCDVD2 A7 PG5 LCDVD3 C8 PG6 LCDVD4 B8 PG7 LCDVD5 C4 PH0 ETHERRX3 A3 PH1 ETHERRXDV B4 PH2 ETHERRXCLK C5 PH3 ETHERTXER D6 PH4 ETHERTX0 A4 PH5 ETHERTX1 B5 PH6 ETHERTX2 C6 PH7 ETHERTX3 D3 PI0 ETHERMDC B1 PI1 ETHERMDIO B2 PI2 ETHERCOL D4 PI3 ETHERCRS C3 PI4 ETHERRXER A1 PI5 ETHERRX0 A2 PI6 ETH...

Page 278: ...LCDVD13 C12 PL4 D28 A14 PL5 D29 B14 PL6 D30 C14 PL7 D31 C11 PN0 D26 A13 PN1 D27 R12 PN2 D24 P11 PN3 D25 H2 AN3 LR Y PJ0 H3 AN4 WIPER PJ1 G1 AN9 PJ2 G2 AN2 LL Y PJ3 G3 AN8 PJ4 F1 AN5 PJ5 INT5 E1 AN7 PJ6 INT6 F3 AN6 PJ7 INT7 L16 nCS0 PM0 L15 nCS1 PM1 M16 nCS2 PM2 L14 nCS3 PM3 J15 nBLE0 PM4 J14 nBLE1 PM5 K16 nBLE2 PM6 K15 nBLE3 PM7 Table 8 2 LH79524 GPIO Multiplexing Cont d CABGA NO AT RESET MULTIPLE...

Page 279: ...Q nUARTRTS0 42 PB2 SSPFRM I2SWS 41 PB3 SSPCLK I2SCLK 40 PB4 SSPRX I2SRXD UARTRX1 UARTIRRX1 39 PB5 SSPTX I2STXD UARTTX1 UARTIRTX1 38 PB6 INT0 UARTRX0 UARTIRRX0 37 PB7 INT1 UARTTX0 UARTIRTX0 60 PC0 A16 59 PC1 A17 58 PC2 A18 56 PC3 A19 55 PC4 A20 54 PC5 A21 53 PC6 A22 nFWE 52 PC7 A23 nFRE 90 PD0 D8 89 PD1 D9 88 PD2 D10 87 PD3 D11 85 PD4 D12 84 PD5 D13 83 PD6 D14 82 PD7 D15 141 PE0 LCDLP LCDHRLP 139 P...

Page 280: ...169 PH2 ETHERRXCLK 167 PH3 ETHERTXER 166 PH4 ETHERTX0 165 PH5 ETHERTX1 164 PH6 ETHERTX2 163 PH7 ETHERTX3 4 PI0 ETHERMDC 2 PI1 ETHERMDIO 1 PI2 ETHERCOL 176 PI3 ETHERCRS 175 PI4 ETHERRXER 174 PI5 ETHERRX0 173 PI6 ETHERRX1 172 PI7 ETHERRX2 20 AN3 LR Y PJ0 19 AN4 WIPER PJ1 18 AN9 PJ2 17 AN2 LL Y PJ3 16 AN8 PJ4 15 AN5 PJ5 INT5 13 AN7 PJ6 INT6 12 AN6 PJ7 INT7 104 nCS0 PM0 103 nCS1 PM1 102 nCS2 PM2 100 n...

Page 281: ... and H 0xFFFDC000 Ports I and J 0xFFFDB000 Ports K and L 0xFFFDA000 Port M and N 0xFFFD9000 As Port J is an input only port the location at base 0xFFFDB000 with an offset of 0x0C which would be the space for the Port J Data Direction Register is reserved However output only Port M does have a Data Direction Register at location 0xFFFD9000 with an offset of 0x08 and must be programmed before use Ta...

Page 282: ...ut values from the Port M pins Table 8 5 P1DRx Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PORT_DATA RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW ADDR Port A 0xFFFDF000 0x00 Port C 0xFFFDE000 0x00...

Page 283: ...rt J pins Table 8 7 P2DRx Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PORT_DATA RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW ADDR Port B 0xFFFDF000 0x04 Port D 0xFFFDE000 0x04 Port F 0xFFFDD000 0x...

Page 284: ...O RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PORT_DIRECTION RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW ADDR Port A 0xFFFDF000 0x08 Port C 0xFFFDE000 0x08 Port E 0xFFFDD000 0x08 Port G 0xFFFDC000 0x08 Port I 0xFFFDB000 0x08 Port K 0xFFFDA000 0x08 LH79524 Only Port M 0xFFFD9000 0x08 Bits 7 and 6 LH79524 Only Table 8 ...

Page 285: ... 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PORT_DIRECTION RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW ADDR Port B 0xFFFDF000 0x0C Port D 0xFFFDE000 0x0C Port F 0xFFFDD000 0x0C Port H 0xFFFDC000 0x0C Port L 0xFFFDA000 0x0C LH79524 Only Port N 0xFFFD9000 0x0C LH79524 Only Table 8 12 P2DD...

Page 286: ...General Purpose Input Output LH79524 LH79525 User s Guide 8 12 Version 1 0 ...

Page 287: ...s s and the fast mode with data rates up to 400 Mbits s Communication with devices in the fast mode as well as the standard mode if both are attached to the bus The I2C Module block diagram appears in Figure 9 1 Figure 9 1 I2C Module Block Diagram START STOP ARBITRATION CONTROL IN OUT DATA SHIFT REGISTER ADDRESS COMPARE CLOCK CONTROL HCLK SCL SDA REGISTERS APB REGISTER INTERFACE INTERRUPT LH79525 ...

Page 288: ...data or receive data from the slave The slave will then send an acknowl edge ACK pulse after the address and R W bit is received to notify the master that the slave has received the request If the master master transmitter is writing to the slave slave receiver the receiver will receive a byte of data This transaction will continue until the master terminates the transmission with a stop condition...

Page 289: ...k LCNT ROUND_UP MIN_SCL_LOW time HCLK frequency k ROUND_UP means to round all fractions up to the next highest integer The LOW count is calculated in the same way Permissible values for the parameters in the equations are found inTable 9 1 Example timing results appear in Table 9 2 Table 9 1 I2C Clock Parameters VALUE 400 kbit s 100 kbits s k constant 4 3 MIN_SCL_HIGH 0 6 μs 4 0 μs MIN_SCL_LOW 1 3...

Page 290: ...errupts Nor do any following data transactions In 10 bit addressing mode the address is transferred in two bytes If the first transfer con taining the most significant address bits matches the most significant bits of the Slave address an interrupt will be generated on both halves of the address If the second part of the address does not match the ICSTAT RXABORT bit is set informing the interrupt ...

Page 291: ...sfer Interrupts set the ICSTAT INT bit Before the interrupt routine is exited this bit must be cleared by reading the ICSTAT register In address and repeat START transactions reading the ICDATA and ICSTAT registers is all that is required of the interrupt handler since address comparisons are performed in hardware 9 1 4 Master Mode Master mode is similar to Slave mode from an interrupt handling po...

Page 292: ...ule is 0xFFFC5000 Table 9 3 summarizes the I2C Module registers Table 9 3 I2 C Register Summary ADDRESS OFFSET NAME DESCRIPTION 0x00 ICCON Configuration Register 0x04 ICSAR Slave Address Register 0x08 ICUSAR Upper Slave Address Register 0x0C ICDATA Data Register 0x10 ICHCNT Clock High Period Count Register 0x14 ICLCNT Clock Low Period Count Register 0x18 Reserved Do Not Access 0x1C ICSTAT Status R...

Page 293: ...gnal is not driven LOW by the Slave with which the I2C Module is communicating Under those conditions this bit is used to define whether or not a STOP Condi tion is generated after each bus transaction or not 1 No STOP Condition is generated 0 An I2 C STOP Condition is generated after each bus transaction 6 RWC Read Write Control Only active in Master mode it specifies direction for data transfers...

Page 294: ...C Module Mode The I2 C Module Mode field sets the operating mode of the I2 C Module 11 I2 C Master Mode 10 Bit addressing 10 I2 C Master Mode 7 Bit addressing 01 I2 C Slave Mode 10 Bit addressing 00 I2 C Slave Mode 7 Bit addressing Table 9 6 ICSAR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO ...

Page 295: ... 31 8 Reserved Reading returns 0 Write the reset value 7 3 UPPERAD Upper Address This field is only used for 10 bit mode When using 10 bit mode this field must be programmed to 0b11110 When using 7 bit mode this field must be programmed to 0b00000 which is the reset value 2 1 SLAD89 Slave Address Bits 9 8 This field contains the upper 2 bits of the 10 bit slave address This field is not used in 7 ...

Page 296: ...mber The HIGH time is ICHCNT 3 HCLK periods in 100 kbit s mode and ICHCNT 4 HCLK cycles in 400 kbit s mode The ICHCNT Register must be programmed before any I2 C bus transac tion can take place to insure proper timing Table 9 14 ICLCNT Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15...

Page 297: ...e The I2 C Module is in 10 bit Slave mode and the upper address bits matched but the lower address bits did not 1 Master Mode The upper and lower address bits match but a restart was issued by the Master in Master receive mode and the repeated upper address does not match 0 No Receive Abort 5 TXABORT Transmit Abort This bit indicates a Transmit fault This bit remains 1 until the ICSTAT Register is...

Page 298: ...received on the I2 C bus and written into the ICDATA register 0 No address or data byte received 0 INTR Interrupt This bit indicates the source of the interrupt condition This bit remains 1 until reset by software The source of the interrupt can be A data byte has been received on the I2 C bus and written to ICDATA A Stop condition has been detected The FULL flag is 1 In Master mode when the TXABO...

Page 299: ...th next entry written to TX FIFO WS value associated with next entry read from RX FIFO Ability to invert WS state Ability to invert the bit clock Supports frame size of 16 bits only Any other frame size will result in a frame size error Each frame transmits starting with the most significant bit Master and Slave modes supported A single combined interrupt is generated as an OR function of the indi...

Page 300: ...0 1 FRAME DELAY SUPPRESSION LOGIC 1 CLOCK DELAY SLAVE CLOCK ENABLE STROBE CONVERSION I2S LEVEL SSP PULSE SLAVE CLOCK ENABLE MASTER SLAVE SSP I2S MODE TXFIFO UNDERUN SSPTXD MASTER CLOCK ENABLE SLAVE CLOCK ENABLE M S I2S SSP SSPTX_I2STXD_OUT SSP I2S MODE SSP_I2S_OE_n SSPFSS_I2SWS_IN SLAVE SSPOE_n WSDEL SSP I2 S MODE SSPFSSIN SLAVE SSP I2 S SSP I2 S 0 1 FRAME DELAY SSPTX_I2STXD_OUT MASTER CLOCK ENABL...

Page 301: ...he SSP Chapter The I2S format is an audio standard made popular by Phillips Semiconductor Figure 10 2 shows the Texas Instruments DSP format for continuous transfers The I2S frame format is described in the I2S Bus specification published by Phillips Semi conductors An example I2 S transaction is shown in Figure 10 3 Figure 10 2 TI SSP Frame Format Figure 10 3 I2S Format SSPCLK SSPFRM SSPTX SSPRX ...

Page 302: ...SP is altered by the I2S Converter to enable the transmit data pad whenever the I2S is enabled If the I2S Converter is disabled then the output enable passes unchanged through the I2 S Converter 10 1 2 Driving Latching Edges The SSP and any device connected to it is expected to drive data and the frame pulse on the rising edge of the clock and latch both on the falling edge of the clock The I2 S S...

Page 303: ...P It is delayed by one clock and then transmitted on the PB5 SSPTX I2STXD UARTTX0 UARTIRTX0 pin Note that when in master mode the I2 S Converter requires that the SSP operate in TI con tinuous mode If the transmit FIFO is starved the SSP will operate in single word transfer mode in which is stops generating SSPCLKOUT and SSPFSSOUT as soon as the transfer of the last word in the FIFO has completed ...

Page 304: ... generating a pulse to the SSP for every edge detected on PB2 SSPFRM I2SWS If WSDEL is set to 0 then the pulse is delayed by 1 clock In this case the data cannot be received from the SSP and transmitted to the external CODEC in time as depicted by Figure 10 7 For this reason the data received from the SSP in slave mode is delayed by the I2S converter before being transmitted on the PB5 SSPTX I2STX...

Page 305: ...cted by Figure 10 9 For this reason the data received from the external CODEC in slave mode is delayed by the I2S converter before being transmitted to the SSP on SSPTXD This results in a one frame lag in the reception of data in master mode regardless of the value of WSDEL Until the delay pipe is filled the SSP will receive a logic low on SSPRXD causing the first two entries in the SSP Receive FI...

Page 306: ...iagram LH79525 99 SSP MASTER EXTERNAL CODEC SLAVE I2SCLKOUT I2S CONVERTER MASTER I2SFSSOUT SCK WS SD I2SRXD SSPCLKOUT SSPFSSOUT SSPTXD I2SFSSOUT WSDEL 0 I2SFSSOUT WSDEL 1 ACTUAL SSPRXD I2SCLKOUT SSPFSSOUT EXPECTED SSPRXD I2SRXD MSB1 14 1 2 1 2 14 14 1 2 1 1 14 1 14 14 1 LSB1 MSB2 MSB3 MSB1 LSB2 MSB4 LSB3 MSB1 MSB2 MSB3 MSB2 LSB1 MSB4 LSB3 LSB2 LSB1 LH79525 100 ...

Page 307: ...nt to the SSP This conversion is accomplished by generating a pulse to the SSP for every edge detected on PB2 SSPFRM I2SWS If WSDEL is 0 the pulse is delayed by one clock The data received by the I2S converter from the external CODEC is delayed by one clock and sent to the SSP on SSPRXD Figure 10 11 I2S Slave Mode Reception Block Diagram Figure 10 12 I2 S Slave Mode Reception Timing Diagram LH7952...

Page 308: ... that known data be sent during a TXIFO Underrun Therefore asserting SSPFSSIN will be suppressed during a TXFIFO Underrun while the I2 S Converter is enabled Additionally a logic 0 will be fed into the I2S Converter Frame Delay pipe so that any remaining valid data is flushed out followed by logic 0 When the I2 S Converter is operating in master mode The suppression of SSPFSSIN and forcing 0 on th...

Page 309: ... the SSP Protocol Error Interrupt This Interrupt is asserted when the SSP and I2S are enabled and the SSP is configured for the wrong frame length This is a new inter rupt and only applies to I2S transactions 10 1 7 2 External Codec Protocol Error Interrupt ECPE is the External Codec Protocol Error Interrupt This Interrupt is asserted when the I2S is operating in slave mode and a frame is transmit...

Page 310: ...un Interrupt This interrupt is asserted when the FIFO is already full and an additional data frame is received causing an overrun of the FIFO Data is over written in the Shift Register but not the FIFO This interrupt originates in the SSP 10 1 7 7 Receive Timeout Interrupt SSPRXTOINTR is the Receive Timeout Interrupt This interrupt is asserted if the receive FIFO does not generate a further servic...

Page 311: ...18 through 0xFFF are reserved and must not be used during normal operation Table 10 1 shows the memory mapping Table 10 1 I2S Converter Register Summary ADDRESS OFFSET NAME DESCRIPTION 0x000 CTRL Control Register 0x004 STAT Status Register 0x008 IMSC Interrupt Mask Set and Clear Register 0x00C RIS Raw Interrupt Status register 0x010 MIS Masked Interrupt Status Register 0x014 ICR Interrupt Clear Re...

Page 312: ...PTION 31 6 Reserved Reading returns 0 Write the reset value 5 LOOP Loopback Mode Applies only to I2 S Transactions Note that two frames of 0x0000 will still be received in master mode 1 Transmit and Receive internally connected for Loopback Mode 0 Normal operation 4 CLKINV Clock Invert Applies only to I2S Transactions Inverts the polarity of the SSPCLK or I2SCLK which is output on the PB3SSPCLK I2...

Page 313: ...in cides with the MSB of the data If WSDEL 1 the frame input is passed to the SSP without additional delay 10 2 2 1 2 Implementation of WSINV As seen in Table 10 4 if the WSINV 0 a logic low on the PB2 SSPFRM I2SWS pin indi cates that the left channel is transmitting while a logic high indicates that the right channel is transmitting If the WSINV bit is set then a logic low on the PB2 SSPFRM I2SWS...

Page 314: ...eceive FIFO Full From SSP SR RFF bit 1 The Receive FIFO is full 0 The Receive FIFO is not full 6 RFE Receive FIFO Empty 1 The Receive FIFO is empty 0 The Receive FIFO is not empty 5 TFF Transmit FIFO Full 1 The Transmit FIFO is full 0 The Transmit FIFO is not full 4 TFE Transmit FIFO Empty From SSP SR TFE bit 1 The Transmit FIFO is empty 0 The Transmit FIFO is not empty 3 TXWS WS value for TX word...

Page 315: ...ion interrupt enabled 0 Master Mode Protocol Error condition interrupt is masked 5 ECPEM External Codec Protocol Error mask 1 Slave Mode Protocol Error condition interrupt enabled 0 Slave Mode Protocol Error condition interrupt is masked 4 TXUEM Transmit Underrun Error mask 1 Tx Underrun condition interrupt enabled 0 Tx Underrun condition interrupt is masked 3 TXIM Transmit FIFO Interrupt mask Fro...

Page 316: ... 0xFFFC8000 0x00C Table 10 10 RIS Register Definitions BITS NAME DESCRIPTION 31 7 Reserved Reading returns 0 Write the reset value 6 SSPPERIS SSP Protocol Error raw interrupt status Indicates that the SSP is configured for a data size other than 16 bits Applies only to I2 S transactions Applies to both Slave and Master Mode operation 5 ECPERIS External Codec Protocol Error raw interrupt status Ind...

Page 317: ...NAME DESCRIPTION 31 7 Reserved Reading returns 0 Write the reset value 6 SSPPEMIS SSP Protocol Error masked interrupt status Gives the Master Mode Protocol Error masked interrupt state 5 ECPEMIS External Codec Protocol Error masked interrupt status Gives the Slave Mode Protocol Error masked interrupt state 4 TXUEMIS Transmit Underrun Error masked interrupt status Gives the Transmit Underrun Error ...

Page 318: ... RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD SSPPEC ECPEC TXUEC RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO WO WO WO RO RO RO RO ADDR 0xFFFC8000 0x014 Table 10 14 ICR Register Definitions BITS NAME DESCRIPTION 31 7 Reserved Reading returns 0 Write the reset value 6 SSPPEC SSP Protocol Error interrupt clear Clears the SSP Protocol Error Interrupt 5 ECPEC External C...

Page 319: ...l down resistors on certain pins of the chip 11 1 Theory of Operation The I O Configuration IOCON is an AMBA slave block that connects to the APB It provides registers for programming pin muxing and for controlling the pull up and pull down resistors on certain pins of the chip These registers should be programmed before any others so that pins are correctly configured before enabling functional b...

Page 320: ...x20 MUXCTL5 Muxing Control 5 For pins from PA1 INT3 UARTTX2 UARTIRTX2 to PB2 SSPFRM 0x24 RESCTL5 Resistor Control 5 Assignment for pins from PA1 INT3 UARTTX2 UARTIRTX2 to PB2 SSPFRM 0x28 MUXCTL6 Muxing Control 6 For pins from PB1 DREQ nUARTRTS0 to PB0 nDACK nUARTCTS0 0x2C RESCTL6 Resistor Control 6 Assignment for pins from PB1 DREQ nUARTRTS0 to PB0 nDACK nUARTCTS0 0x30 MUXCTL7 Muxing Control 7 For...

Page 321: ...or pins from PE2 LCDPS to PF6 LCDEN LCDSPL 0xA0 MUXCTL21 Muxing Control 21 For pins from PF5 LCDVD11 to PF2 LCDVD8 0xA4 RESCTL21 Resistor Control 21 Assignment for pins from PF5 LCDVD11 to PF2 LCDVD8 0xA8 MUXCTL22 Muxing Control 22 For pins from PF1 LCDVD7 to PG2 LCDVD0 0xAC RESCTL22 Resistor Control 22 Assignment for pins from PF1 LCDVD7 to PG2 LCDVD0 0xB0 MUXCTL23 Muxing Control 23 For pins from...

Page 322: ...T 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PI2 PI1 PI0 PL1 PL0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x00 Table 11 3 MUXCTL1 Fields BIT NAME DESCRIPTION 31 10 Reserved Reading returns 0 Write the reset value 9 8 PI2 PI2 ETHERCOL Assignment 00 PI2 01 ETHERCOL 10 Reserved 11 Reserved 7 6 PI1 PI1 ETHERMDIO Assignment 00 PI1 01 ETHE...

Page 323: ...0 0 0 0 1 1 0 0 1 0 1 0 1 RW RO RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x04 Table 11 5 RESCTL1 Fields BIT NAME DESCRIPTION 31 10 Reserved Reading returns 0 Write the reset value 9 8 PI2 Pin PI2 ETHERCOL Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 7 6 PI1 Pin PI1 ETHERMDIO Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pul...

Page 324: ...0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW ADDR 0xFFFE5000 0x10 Table 11 7 MUXCTL3 Fields BIT NAME DESCRIPTION 31 2 Reserved Reading returns 0 Write the reset value 1 0 INT4 CTCLK INT4 BATCNTL Pin Assignment 00 CTCLK 01 INT4 10 BATCNTL 11 Reserved Table 11 8 RESCTL3 Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO...

Page 325: ... 0 0 0 0 0 0 0 RW RO RO RO RO RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x18 Table 11 11 MUXCTL4 Fields BIT NAME DESCRIPTION 31 12 Reserved Reading returns 0 Write the reset value 11 10 PA7 PA7 CTCAP2B CTCMP2B SCL Assignment 00 PA7 01 CTCAP2B 10 CTCMP2B 11 SCL 9 8 PA6 PA6 CTCAP2A CTCMP2A SDA Assignment 00 PA6 01 CTCAP2A 10 CTCMP2A 11 SDA 7 6 PA5 PA5 CTCAP1B CTCMP1B Assignment 00 PA5 01 C...

Page 326: ... 11 13 RESCTL4 Fields BIT NAME DESCRIPTION 31 12 Reserved Reading returns 0 Write the reset value 11 10 PA7 Pin PA7 CTCAP2B CTCMP2B SCL Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 9 8 PA6 Pin PA6 CTCAP2A CTCMP2A SDA Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 7 6 PA5 Pin PA5 CTCAP1B CTCMP1B Resistor Assignment 00 No Pull...

Page 327: ...Table 11 15 MUXCTL5 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PA1 PA1 INT3 UARTTX2 UARTIRTX2 Assignment 00 PA1 01 INT3 10 UARTTX2 11 UARTIRTX2 13 12 PA0 PA0 INT2 UARTRX2 UARTIRRX2 Assignment 00 PA0 01 INT2 10 UARTRX2 11 UARTIRRX2 11 10 PB7 PB7 INT1 UARTTX0 UARTIRTX0 Assignment 00 PB7 01 INT1 10 UARTTX0 11 UARTIRTX0 9 8 PB6 PB6 INT0 UARTRX0 UARTIRRX0 A...

Page 328: ...W RW RW RW RW RW RW ADDR 0xFFFE5000 0x24 Table 11 17 RESCTL5 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PA1 Pin PA1 INT3 UARTTX2 UARTIRTX2 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 13 12 PA0 Pin PA0 INT2 UARTRX2 UARTIRRX2 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 11 10 PB...

Page 329: ...0 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 3 2 PB3 Pin PB3 SSPCLK Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 1 0 PB2 Pin PB2 SSPFRM Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved Table 11 17 RESCTL5 Fields Cont d BIT NAME DESCRIPTION ...

Page 330: ...0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PB1 PB0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW ADDR 0xFFFE5000 0x28 Table 11 19 MUXCTL6 Fields BIT NAME DESCRIPTION 31 4 Reserved Reading returns 0 Write the reset value 3 2 PB1 PB1 DREQ nUARTRTS0 Assignment 00 PB1 01 DREQ 10 n...

Page 331: ... 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PB1 PB0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW ADDR 0xFFFE5000 0x2C Table 11 21 RESCTL6 Fields BIT NAME DESCRIPTION 31 4 Reserved Reading returns 0 Write the reset value 3 2 PB1 Pin PB1 DREQ nUARTRTS0 Resistor Assignment 00 No Pull Down or Pull...

Page 332: ... 7 6 5 4 3 2 1 0 FIELD PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x30 Table 11 23 MUXCTL7 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PC7 PC7 A23 nFRE Assignment 00 PC7 01 A23 10 nFRE 11 Reserved 13 12 PC6 PC6 A22 nFWE Assignment 00 PC6 01 A22 10 nFWE 11 Reser...

Page 333: ... 0 11 15 5 4 PC2 PC2 A18 Assignment 00 PC2 01 A18 10 Reserved 11 Reserved 3 2 PC1 PC1 A17 Assignment 00 PC1 01 A17 10 Reserved 11 Reserved 1 0 PC0 PC0 A16 Assignment 00 PC0 01 A16 10 Reserved 11 Reserved Table 11 23 MUXCTL7 Fields Cont d BIT NAME DESCRIPTION ...

Page 334: ...1 0 1 0 1 0 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x34 Table 11 25 RESCTL7 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PC7 Pin PC7 A23 nFRE Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 13 12 PC6 Pin PC6 A2nFWE Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Re...

Page 335: ...ll Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 3 2 PC1 Pin PC1 A17 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 1 0 PC0 Pin PC0 A16 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved Table 11 25 RESCTL7 Fields Cont d BIT NAME DESCRIPTION ...

Page 336: ... 4 3 2 1 0 FIELD PN3 PN2 PD7 PK7 PD6 PK6 PD5 PK5 LH79525 RESET 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 LH79524 RESET 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x48 Table 11 27 MUXCTL10 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PN3 PN3 D25 Assignment LH79524 Only 00 PN3 01 D25 10 Reserved 11 Reserved 13 ...

Page 337: ...K6 PK6 D22 Assignment LH79524 Only 00 PK6 01 D22 10 Reserved 11 Reserved 3 2 PD5 PD5 D13 Assignment 00 PD5 01 D13 10 Reserved 11 Reserved 1 0 PK5 PK5 D21 Assignment LH79524 Only 00 PK5 01 D21 10 Reserved 11 Reserved Table 11 27 MUXCTL10 Fields Cont d BIT NAME DESCRIPTION ...

Page 338: ...ESET 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x4C Table 11 29 RESCTL10 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PN3 Pin PN3 D25 Resistor Assignment LH79524 Only 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 13 12 PN2 Pin PN2 D24 Resistor Assignment LH79524 Only 00 No Pull Dow...

Page 339: ...l Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 3 2 PD5 Pin PD5 D13 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 1 0 PK5 Pin PK5 D21 Resistor Assignment LH79524 Only 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved Table 11 29 RESCTL10 Fields Cont d BIT NAME DESCRIPTION ...

Page 340: ...12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PD4 PK4 PD3 PK3 PD2 PK2 PK1 PD1 RESET 8 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET 16 Bit 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 RESET 32 Bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x50 Table 11 31 MUXCTL11 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PD4 PD4 D12 Assig...

Page 341: ... D10 10 Reserved 11 Reserved 5 4 PK2 PK2 D18 Assignment LH79524 Only 00 PK2 01 D18 10 Reserved 11 Reserved 3 2 PK1 PK1 D17 Assignment LH79524 Only 00 PK1 01 D17 10 Reserved 11 Reserved 1 0 PD1 PD1 D9 Assignment 00 PD1 01 D9 10 Reserved 11 Reserved Table 11 31 MUXCTL11 Fields Cont d BIT NAME DESCRIPTION ...

Page 342: ...1 PD1 RESET 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x54 Table 11 33 RESCTL11 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PD4 Pin PD4 D12 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 13 12 PK4 Pin PK4 D20 Resistor Assignment LH79524 Only 00 No Pull Down or P...

Page 343: ...ll Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 3 2 PK1 Pin PK1 D17 Resistor Assignment LH79524 Only 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 1 0 PD1 Pin PD1 D9 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved Table 11 33 RESCTL11 Fields Cont d BIT NAME DESCRIPTION ...

Page 344: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PK0 PD0 RESET 8 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET 16 Bit 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 RESET 32 Bit 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x58 Table 11 35 MUXCTL12 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the r...

Page 345: ...7 D6 D5 D4 D3 D2 RESET 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x5C Table 11 37 RESCTL12 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PK0 Pin PK0 D16 Resistor Assignment LH79524 Only 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 13 12 PD0 Pin PD0 D8 Resistor Assignment 00 No Pull...

Page 346: ...Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 3 2 D3 Pin PD3 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 1 0 D2 Pin PD2 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved Table 11 37 RESCTL12 Fields Cont d BIT NAME DESCRIPTION ...

Page 347: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD D1 D0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 RW RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW ADDR 0xFFFE5000 0x64 Table 11 39 RESCTL13 Fields BIT NAME DESCRIPTION 31 4 Reserved Reading returns 0 Write the reset value 3 2 D1 Pin D1 Resistor Assignment 00 No Pull Down or Pu...

Page 348: ...79525 RESET 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 LH79524 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x68 Table 11 41 MUXCTL14 Fields BIT NAME DESCRIPTION 31 12 Reserved Reading returns 0 Write the reset value 15 14 nCS3 nCS3 PM3 Assignment 00 nCS3 01 PM3 10 Reserved 11 Reserved 13 12 nCS2 nCS2 PM2 Assignment 00 nCS2 01 PM2 10 Reserved 11 Res...

Page 349: ... O Configuration Version 1 0 11 31 3 2 nBLE2 nBLE2 PM6 Assignment 00 nBLE2 01 PM6 10 Reserved 11 Reserved 1 0 nBLE1 nBLE3 PM5 Assignment 00 nBLE1 01 PM5 10 Reserved 11 Reserved Table 11 41 MUXCTL14 Fields Cont d BIT NAME DESCRIPTION ...

Page 350: ...0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW ADDR 0xFFFE5000 0x70 Table 11 43 MUXCTL15 Fields BIT NAME DESCRIPTION 31 2 Reserved Reading returns 0 Write the reset value 1 0 nBLE0 nBLE0 PM4 Assignment 00 nBLE0 01 PM4 10 Reserved 11 Reserved Table 11 44 RESCTL15 Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R...

Page 351: ...5 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD SDCLK RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW ADDR 0xFFFE5000 0x84 Table 11 47 RESCTL17 Fields BIT NAME DESCRIPTION 31 2 Reserved Reading returns 0 Write the reset value 1 0 SDCLK...

Page 352: ... 1 0 FIELD PE7 PE6 PL7 PE5 PL6 D30 PE4 PE3 PL5 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET 32 Bit 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x90 Table 11 49 MUXCTL19 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PE7 PE7 nWAIT nDEOT Assignment 00 PE7 01 nWAIT 10 nDEOT 11 Reserved 13 12 PE6 PE6 LCDVEE...

Page 353: ...E4 LCDSPLEN LCDREV Assignment 00 PE4 01 LCDSPLEN 10 LCDREV 11 Reserved 3 2 PE3 PE3 LCDCLS Assignment 00 PE3 01 LCDCLS 10 Reserved 11 Reserved 1 0 PL5 PL5 D29 Assignment LH79524 Only 00 PL5 01 D29 10 Reserved 11 Reserved Table 11 49 MUXCTL19 Fields Cont d BIT NAME DESCRIPTION ...

Page 354: ...1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x94 Table 11 51 RESCTL19 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PE7 Pin PE7 nWAIT nDEOT Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 13 12 PE6 Pin PE6 LCDVEEN LCDMOD Resistor Assignment 00 No Pull Down or Pull Up...

Page 355: ...Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 3 2 PE3 Pin PE3 LCDCLS Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 1 0 PL5 Pin PL5 D29 Resistor Assignment LH79524 Only 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved Table 11 51 RESCTL19 Fields Cont d BIT NAME DESCRIPTION ...

Page 356: ...2 1 0 FIELD PE2 PL4 PE1 PN1 PE0 PN0 PF7 PF6 LH79525 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LH79524 RESET 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x98 Table 11 53 MUXCTL20 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PE2 PE2 LCDPS Assignment 00 PE2 01 LCDPS 10 Reserved 11 Reserved 13 12 PL4 PL4 D28...

Page 357: ... PN0 D26 Assignment LH79524 Only 00 PN0 01 D26 10 Reserved 11 Reserved 3 2 PF7 PF7 LCDFP LCDSPS Assignment 00 PF6 01 LCDFP 10 LCDSPS 11 Reserved 1 0 PF6 PF6 LCDEN LCDSPL Assignment 00 PF6 01 LCDEN 10 LCDSPL 11 Reserved Table 11 53 MUXCTL20 Fields Cont d BIT NAME DESCRIPTION ...

Page 358: ...SET 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x96 Table 11 55 RESCTL20 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PE2 Pin PE2 LCDPS Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 13 12 PL4 Pin PL4 D28 Resistor Assignment LH79524 Only 00 No Pull Down or Pull Up...

Page 359: ...Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 3 2 PF7 Pin PF7 LCDFP LCDSPS Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 1 0 PF6 Pin PF6 LCDEN LCDSPL Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved Table 11 55 RESCTL20 Fields Cont d BIT NAME DESCRIPTION ...

Page 360: ...D PF5 PL3 PF4 PL2 PF3 PF2 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0xA0 Table 11 57 MUXCTL21 Fields BIT NAME DESCRIPTION 31 12 Reserved Reading returns 0 Write the reset value 11 10 PF5 PF5 LCDVD11 Assignment 00 PF5 01 LCDVD11 10 Reserved 11 Reserved 9 8 PL3 PL3 LCDVD13 Assignment LH79524 Only 00 PL3 01 LCDVD13 10 Reserved 11 Reserved...

Page 361: ...RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0xA4 Table 11 59 RESCTL21 Fields BIT NAME DESCRIPTION 31 12 Reserved Reading returns 0 Write the reset value 11 10 PF5 Pin PF5 LCDVD11 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 9 8 PL3 Pin PL3 LCDVD13 Resistor Assignment LH79524 Only 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 7 6 PF4 Pin PF4 ...

Page 362: ... 1 0 FIELD PF1 PF0 PG7 PG6 PG5 PG4 PG3 PG2 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0xA8 Table 11 61 MUXCTL22 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PF1 PF1 LCDVD7 Assignment 00 PF1 01 LCDVD7 10 Reserved 11 Reserved 13 12 PF0 PF0 LCDVD6 Assignment 00 PF0 01 LCDVD6 10 Reserved 11 Reserv...

Page 363: ... 4 PG4 PG4 LCDVD2 Assignment 00 PG4 01 LCDVD2 10 Reserved 11 Reserved 3 2 PG3 PG3 LCDVD1 Assignment 00 PG3 01 LCDVD1 10 Reserved 11 Reserved 1 0 PG2 PG2 LCDVD0 Assignment 00 PG2 01 LCDVD0 10 Reserved 11 Reserved Table 11 61 MUXCTL22 Fields Cont d BIT NAME DESCRIPTION ...

Page 364: ...0 1 0 1 0 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0xAC Table 11 63 RESCTL22 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PF1 Pin PF1 LCDVD7 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 13 12 PF0 Pin PF0 LCDVD6 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reser...

Page 365: ... Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 3 2 PG3 Pin PG3 LCDVD1 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 1 0 PG2 Pin PG2 LCDVD0 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved Table 11 63 RESCTL22 Fields Cont d BIT NAME DESCRIPTION ...

Page 366: ...1 PG0 PH7 PH6 PH5 PH4 PH3 PH2 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0xB0 Table 11 65 MUXCTL23 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PG1 PG1 ETHERTXCLK Assignment 00 PG1 01 ETHERTXCLK 10 Reserved 11 Reserved 13 12 PG0 PG0 ETHERTXEN Assignment 00 PG0 01 ETHERTXEN 10 Reserved 11 Reser...

Page 367: ...4 ETHERTX0 Assignment 00 PH4 01 ETHERTX0 10 Reserved 11 Reserved 3 2 PH3 PH3 ETHERTXER Assignment 00 PH3 01 ETHERTXER 10 Reserved 11 Reserved 1 0 PH2 PH2 ETHERRXCLK Assignment 00 PH2 01 ETHERRXCLK 10 Reserved 11 Reserved Table 11 65 MUXCTL23 Fields Cont d BIT NAME DESCRIPTION ...

Page 368: ... 0 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0xB4 Table 11 67 RESCTL23 Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 PG1 Pin PG1 ETHERTXCLK Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 13 12 PG0 Pin PG0 ETHERTXEN Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reser...

Page 369: ...wn or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 3 2 PH3 Pin PH3 ETHERTXER Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 1 0 PH2 Pin PH2 ETHERRXCLK Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved Table 11 67 RESCTL23 Fields Cont d BIT NAME DESCRIPTION ...

Page 370: ...O RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0xB8 Table 11 69 MUXCTL24 Fields BIT NAME DESCRIPTION 31 14 Reserved Reading returns 0 Write the reset value 13 12 PH1 PH1 ETHERRXDV Assignment 00 PH1 01 ETHERRXDV 10 Reserved 11 Reserved 11 10 PH0 PH0 ETHERRX3 Assignment 00 PH0 01 ETHERRX3 10 Reserved 11 Reserved 9 8 PI7 PI7 ETHERRX2 Assignment 00 PI7 01 ETHERRX2 10 Reserved 11 Reserved ...

Page 371: ...NAME DESCRIPTION 31 14 Reserved Reading returns 0 Write the reset value 13 12 PH1 Pin PH1 ETHERR XDV Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 11 10 PH0 Pin PH0 ETHERRX3 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserved 9 8 PI7 Pin PI7 ETHERRX2 Resistor Assignment 00 No Pull Down or Pull Up 01 Pull Down 10 Pull Up 11 Reserve...

Page 372: ... 2 1 0 FIELD AN6 AN7 AN5 AN8 AN2 AN9 AN4 AN3 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0xC0 Table 11 73 MUXCTL25 Fields BIT NAME DESCRIPTION 31 16 Reserved Writing to these BIT has no effect Reading returns 0 15 14 AN6 AN6 PJ7 INT7 Assignment 00 AN6 01 PJ7 10 INT7 11 Reserved 13 12 AN7 AN7 PJ6 INT6 Assignment 00 AN7 01 PJ6 10 INT6 11 R...

Page 373: ... AN9 AN9 PJ2 Assignment 00 AN9 01 PJ2 10 Reserved 11 Reserved 3 2 AN4 AN4 WIPER PJ1 Assignment 00 AN4 WIPER 01 PJ1 10 Reserved 11 Reserved 1 0 AN3 AN3 LR Y PJ0 Assignment 00 AN3 LR Y 01 PJ0 10 Reserved 11 Reserved Table 11 73 MUXCTL25 Fields Cont d BIT NAME DESCRIPTION ...

Page 374: ...I O Configuration LH79524 LH79525 User s Guide 11 56 Version 1 0 ...

Page 375: ...t be enabled in the Reset Clock and Power Controller RCPC block programming the PCKLCTRL0 RTC bit to 1 If the RTC is not used program the PCKLCTRL0 RTC bit to 0 and the external 32 768 kHz crystal need not be provided The XTAL32IN signal floats therefore it should be tied LOW Clock generation is discussed in greater detail in Chapter 13 Reset Clock and Power Controller Following reset the RTC is d...

Page 376: ...RTC is reset by nRESETIN or by a software reset 12 1 1 Configuring the RTC for Use To configure the RTC 1 Set the initial counter value by writing the value to the LR This value becomes valid on the next CLK1HZ rising edge 2 Set the interrupt trigger value by writing the value to the MR 3 Clear pending interrupts to eliminate spurious interrupts that may have been gener ated at reset by writing 0x...

Page 377: ...0x10 IMSC Interrupt Mask Set and Clear Register 0x14 RIS Raw Interrupt Status Register 0x18 MIS Masked Interrupt Status Register 0x1C ICR Interrupt Clear Register 0x20 0xFF Reserved Do not access Table 12 2 DR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RTCDR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 ...

Page 378: ... Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RTCMR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RTCMR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE0000 0x04 Table 12 5 MR Fields BIT NAME DESCRIPTION 31 0 RTCMR RTC Match Register C...

Page 379: ... Fields BIT NAME DESCRIPTION 31 1 Reserved Unpredictable values when read Write the reset value 0 START RTC Start The RTC can be enabled by writing a 1 to this bit Once enabled any writes to this bit have no effect on the RTC until a system reset Reading returns the status of the RTC 1 RTC enabled 0 RTC disabled read only Table 12 10 IMSC Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1...

Page 380: ...O RO RO ADDR 0xFFFE0000 0x14 Table 12 13 RIS Fields BITS NAME DESCRIPTION 31 1 Reserved Reading returns 0 Values written cannot be read 0 RIS Raw Interrupt Status Contains the raw state prior to masking of the RTC Interrupt 1 RTC Interrupt asserted 0 RTC Interrupt not asserted Table 12 14 MIS Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R...

Page 381: ...7 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD ICR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO ADDR 0xFFFE0000 0x1C Table 12 17 ICR Fields BITS NAME DESCRIPTION 31 1 Reserved Unpredictable values when read Values written cannot be read 0 ICR Interrupt Clea...

Page 382: ...m HCLK prescaled by 1 2 4 8 16 32 64 128 or 256 Generates the Synchronous Serial Port SSPCLK clock from HCLK or the System Clock Oscillator clock prescaled by 1 2 4 8 16 32 or 64 128 or 256 Select the USB clock from HCLK or the USB PLL Clock prescaled by 1 2 or 4 Generates the ADC clock from HCLK or the System Clock Oscillator clock prescaled by 1 2 4 8 16 32 or 64 128 or 256 Provides a selectable...

Page 383: ...mless transition between the old and new frequencies The same protection is not available however when changing the frequency of individual peripheral clocks as a result the peripheral must be disabled before changing frequency The RCPC also manages five Power Modes Active Standby Sleep Stop1 Stop2 Figure 13 1 RCPC Block Diagram LH79525 67 RCPC REGISTERS SYSTEM CLOCK OSCILLATOR 32 768 kHz OSCILLAT...

Page 384: ... cycles after the external reset is released Since the WDT and Soft Reset can be generated only if the System Clock is running the System PLL must be locked If the System PLL is not locked when an external reset is deasserted the RCPC waits until the System PLL acquires lock and holds eight System Clock cycles before releasing the system reset output 13 1 3 Clock Generation The RCPC generates the ...

Page 385: ...tem Clock crystal oscillator To activate the RTC and UART clocks program the PCLKCTRL0 Register The LCD data clock LCDDCLK is generated from the System Clock frequency The SSP and ADC clocks are generated from either the System Clock or the System Clock Oscilla tor clock according to the value programmed in the PCLKSEL1 Register These clocks are prescalable according to the values programmed in th...

Page 386: ...the Ethernet block This clock can be separately enabled disabled but is always the same frequency as HCLK This clock is synchronous to HCLK DMA Clock 50 803 MHz The DMA clock originates in the RCPC and is connected to the DMA block This clock can be separately enabled and disabled but always has the same frequency as HCLK It is synchronous to HCLK External Memory Controller Clock 50 803 MHz The EM...

Page 387: ...xits Standby Mode The RTC oscillator is active as it is in all modes 13 1 4 3 Sleep Mode Sleep Mode stops all System Clocks keeping only the PLLs RTC Oscillator and System Clock Oscillator active This mode is entered when software writes 0b010 to the PWRD WNSEL field of the CTRL Register When an interrupt is received the RCPC exits Sleep Mode and ensures an orderly transition to Active Mode An int...

Page 388: ...writes 0b100 to the PWRDWNSEL field of the CTRL Register When an interrupt is received the RCPC exits Stop2 Mode and ensures an orderly transition to Active Mode An interrupt should be held active until the RCPC exits Stop2 Mode 13 1 4 6 Power Control in JTAG Mode When using JTAG the SoC cannot be placed in a low power mode This SoC will go into the low power mode but is then immediately awakened ...

Page 389: ...Status Clear Register 0x18 SYSCLKPRE System Clock Prescaler Register 0x1C CPUCLKPRE CPU Clock Prescaler Register 0x20 Reserved Do not access 0x24 PCLKCTRL0 Peripheral Clock Control 0 Register 0x28 PCLKCTRL1 Peripheral Clock Control 1 Register 0x2C AHBCLKCTRL AHB Clock Control 0x30 PCLKSEL0 Peripheral Clock Select Register 0 0x34 PCLKSEL1 Peripheral Clock Select Register 1 0x38 Reserved Do not acce...

Page 390: ...reset value 9 LOCK Lock 0 All RCPC registers that are accessible through the APB other than this bit and the INTCLR Register are write protected 1 All RCPC APB accessible registers are write enabled default 8 Reserved Reading returns 0 Write the reset value 7 Reserved Read as 0 Always write 0 Writing a 1 causes unpredictable results 6 5 OUTSEL CLKOUT Source Select Select the source clock for the C...

Page 391: ...ble 13 6 CHIPID Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PARTNO RESET LH79524 0 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 RESET LH79525 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFE2000 0x04 Table 13 ...

Page 392: ...LD REMAP RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW ADDR 0xFFFE2000 0x08 Table 13 9 REMAP Fields BITS NAME DESCRIPTION 31 2 Reserved Reading returns 0 Write the reset value 1 0 REMAP REMAP Remaps external and internal memory system peripher als and registers as shown Figure 13 3 through Figure 13 6 Figure 13 3 Remap 0b00 LH79525 15 ADVANCED HIGH PERFOR...

Page 393: ...EMORY EXTERNAL SDRAM 16KB INTERNAL SRAM BOOT ROM RESERVED 0xFFFFFFFF 0xFFFF1000 0xFFFF0000 0xFFFC0000 0xA0000000 0x80000000 0x60000000 0x40000000 0x20000000 0x00000000 LH79525 17 ADVANCED HIGH PERFORMANCE BUS PERIPHERALS ADVANCED PERIPHERAL BUS PERIPHERALS RESERVED INTERNAL SRAM REMAP 10 EXTERNAL STATIC MEMORY EXTERNAL SDRAM 16KB INTERNAL SRAM BOOT ROM RESERVED 0xFFFFFFFF 0xFFFF1000 0xFFFF0000 0xF...

Page 394: ...9525 18 ADVANCED HIGH PERFORMANCE BUS PERIPHERALS ADVANCED PERIPHERAL BUS PERIPHERALS RESERVED EXTERNAL SRAM nCS0 REMAP 11 EXTERNAL STATIC MEMORY EXTERNAL SDRAM 16KB INTERNAL SRAM BOOT ROM RESERVED 0xFFFFFFFF 0xFFFF1000 0xFFFF0000 0xFFFC0000 0xA0000000 0x80000000 0x60000000 0x40000000 0x20000000 0x00000000 ...

Page 395: ...8 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD SRST RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE2000 0x0C Table 13 11 SOFTRESET Fields BITS NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset valu...

Page 396: ... RSTSTATUS Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD WDTO EXT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFE2000 0x10 Table 13 13 RSTSTATUS Fields BITS NAME DESCRIPTION 31 2 Reserved R...

Page 397: ... BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET RW WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TOCLR EXTCLR RESET RW WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO ADDR 0xFFFE2000 0x14 Table 13 15 RSTSTATUSCLR Fields BITS NAME DESCRIPTION 31 2 Reserved Reads undefined Write 0 only 1 TOCLR Clear WDT Timeout Write 1 to clear the W...

Page 398: ... 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD HDIV RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 RW RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW ADDR 0xFFFE2000 0x18 Table 13 17 SYSCLKPRE Fields BITS NAME DESCRIPTION 31 4 Reserved Reading returns 0 Write the reset value 3 0 HDIV HCLK Divisor Program with the divisor for the H...

Page 399: ...uency Table 13 19 CPUCLKPRE Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD FDIV RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 RW RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW ADDR 0xFFFE2000 0x1C Table 13 20 CPUCLKPRE Fields BITS NAME DESCRIPTION 31...

Page 400: ...6 5 4 3 2 1 0 FIELD RTC U2 U1 U0 RESET 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 RW RO RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE2000 0x24 Table 13 23 PCLKCTRL0 Fields BITS NAME DESCRIPTION 31 10 Reserved Reading returns 0 Write the reset value 9 RTC RTC Clock 1 Disables the RTC input clock 0 Enables the RTC input clock 8 3 Reserved Reading returns 1 Write the reset value 2 U2 UART2 Clock Enab...

Page 401: ... 9 8 7 6 5 4 3 2 1 0 FIELD USB ADC SSP LCD RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 RW RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW ADDR 0xFFFE2000 0x28 Table 13 25 PCLKCTRL1 Fields BITS NAME DESCRIPTION 31 4 Reserved Reading returns 0 Write the reset value 3 USB USB Clock Enables and disables the internal 48 MHz clock to the USB Device peripheral 1 Stops the USB Clock 0 Enables the USB Clock 2 AD...

Page 402: ...RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD LCD USB ETHERNET SDRAM DM A RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW ADDR 0xFFFE2000 0x2C Table 13 27 AHBCLKCTRL Fields BITS NAME DESCRIPTION 31 5 Reserved Reading returns 0 Write the reset value 4 LCD AHB LCD Clock 1 Disables the LCD AHB clock 0 Enables the LCD AHB peripheral clock...

Page 403: ... RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD UART2 UART1 UART0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW ADDR 0xFFFE2000 0x30 Table 13 29 PCLKSEL0 Fields BITS NAME DESCRIPTION 31 3 Reserved Reading returns 0 Write the reset value 2 UART2 UART2 Clock Source 1 System Clock HCLK 0 Crystal oscillator output 1 UART1 ...

Page 404: ... 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD USB ADC SSP RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW ADDR 0xFFFE2000 0x34 Table 13 31 PCLKSEL1 Fields BITS NAME DESCRIPTION 31 4 Reserved Reading returns 0 Write the reset value 3 USB USB Peripheral Clock Source Following reset HC...

Page 405: ...9 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD REVNO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFE2000 0x3C Table 13 33 SILICONREV Fields BITS NAME DESCRIPTION 31 16 Reserved Reading returns 0 Do not write 15...

Page 406: ... RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD LCDDIV RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW ADDR 0xFFFE2000 0x40 Table 13 35 LCDPRE Fields BITS NAME DESCRIPTION 31 8 Reserved Reading returns 0 Write the reset value 7 0 LCDDIV LCD Data Clock Divisor Program w...

Page 407: ... 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD SSPDIV RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW ADDR 0xFFFE2000 0x44 Table 13 38 SSPPRE Fields BITS NAME DESCRIPTION 31 8 Reserved Reading returns 0 Write the reset value 7 0 SSPDIV SSP Divisor...

Page 408: ...19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD ADCDIV RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW ADDR 0xFFFE2000 0x48 Table 13 41 ADCPRE Fields BITS NAME DESCRIPTION 31 8 Reserved Reading returns 0 Write the reset value 7 0 ADCDIV ADC Clock Divis...

Page 409: ... must be programmed to the appropriate divisor following reset see Section 13 2 2 23 Table 13 45 shows the valid combinations for USBDIV and the resulting USB clock fre quency All other USBDIV values are invalid Table 13 43 USBPRE Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 ...

Page 410: ...W RW RW RW ADDR 0xFFFE2000 0x80 Table 13 47 INTCONFIG Fields BITS NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 14 INT7 Configures External Interrupt INT7 00 Configures INT7 to be a LOW level trigger 01 Configures INT7 to be a HIGH level trigger 10 Configures INT7 to be a falling edge trigger 11 Configures INT7 to be a rising edge trigger 13 12 INT6 Configures External...

Page 411: ... trigger active HIGH 10 Configures INT2 to be a falling edge trigger 11 Configures INT2 to be a rising edge trigger 3 2 INT1 Configures External Interrupt INT1 00 Configures INT1 to be a level trigger active LOW 01 Configures INT1 to be a level trigger active HIGH 10 Configures INT1 to be a falling edge trigger 11 Configures INT1 to be a rising edge trigger 1 0 INT0 Configures External Interrupt I...

Page 412: ...O WO WO ADDR 0xFFFE2000 0x84 Table 13 49 INTCLR Fields BITS NAME DESCRIPTION 31 8 Reserved Reading is indeterminate Write the reset value 7 INT7 Clear INT7 Interrupt 1 Clears the active edge triggered interrupt INT7 0 No effect 6 INT6 Clear INT6 Interrupt 1 Clears the active edge triggered interrupt INT6 0 No effect 5 INT5 Clear INT5 Interrupt 1 Clears the active edge triggered interrupt INT5 0 No...

Page 413: ...3 50 CORECONFIG Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CCLK RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO WO WO WO WO WO WO WO WO ADDR 0xFFFE2000 0x88 Table 13 51 CORECONFIG Fields BITS NAME DESCRIPTION 31 2 Reserved...

Page 414: ... 0 1 0 0 0 1 0 1 RW RO RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE2000 0xC0 Table 13 53 SYSPLLCTL Fields BITS NAME DESCRIPTION 31 14 Reserved Reading returns 0 Write the reset value 13 Reserved Reading returns 0 Write 1 only 12 SYSFRANGE System PLL Output Frequency Range Select 1 100 MHz to 304 819 MHz best jitter performance achieved 0 20 MHz to 100 MHz 11 6 SYSPREDIV System PLL Pre ...

Page 415: ... 54 USBPLLCTL Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD USBPDN USBFRANGE USBPREDIV USBLOOPDIV RESET 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 RW RO RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE2000 0xC4 Table 13 55 USBPLLCTL Fields BITS ...

Page 416: ... clock rate Programmable data frame size from 4 to 16 bits Each frame transmits most significant bit first Single combined interrupt is an OR function of the individual interrupt requests Loopback Test Mode 14 1 Theory of Operation The SSP is a master or slave interface for synchronous serial communication with slave peripheral devices that have Motorola SPI National Semiconductor Microwire or Tex...

Page 417: ...ctive LOW and asserted pulled down during the entire frame transmis sion Both formats output data on the falling edge of the clock and latch input data on the rising edge of the clock Table 14 1 Feature Comparison MODE DESCRIPTION DATA TRANSFERS COMMENT SPI Lets the SSP communicate with Motorola SPI compatible devices Full duplex 4 wire synchronous Clock polarity and phase are programmable SSI Let...

Page 418: ... 3 14 1 1 Timing Waveforms Figure 14 1 shows the standard set of SSP timing waveforms Timing values for the call outs on the figure can be found in the Data Sheet Figure 14 1 SSP Timing Waveform Parameters SSPCLK SSPFRM SSPTX SSPRX tOVSSPFRM tOVSSPTX tISSPRX LH79525 21 ...

Page 419: ... and Continuous Modes Figure 14 2 and Figure 14 3 show the Motorola SPI frame format for single data transfers continuous data transfers and when SPH equals 0 or 1 Figure 14 2 Motorola SPI Frame Format Continuous Transfer Figure 14 3 Motorola SPI Frame Format with SPH 0 LH79525 74 SSPCLK SSPFRM SSPTXD SSSRXD 4 to 16 BITS LSB NOTE SPH 0 SPO 0 LSB MSB MSB SSPFRM SSPRX from slave SSPTX from master SS...

Page 420: ...format the SSP outputs data on the rising edge of the clock and latches input data on the rising edge of the clock Figure 14 4 shows the Texas Instruments DSP format for a single transfer Figure 14 5 shows the same format for continuous transfers Figure 14 4 Texas Instruments Synchronous Serial Frame Format Single Transfer Figure 14 5 Texas Instruments Synchronous Serial Frame Format Continuous Tr...

Page 421: ...the requested data The returned data can be 4 to 16 bits long making the total frame 13 to 25 bits long During reception data goes through a serial to parallel conversion before being placed into the receive FIFO The data is then read out via the AMBA APB interface In the Microwire mode the SSP slave samples the first bit of receive data on the rising edge of SSPCLK after SSPRX has gone LOW Master...

Page 422: ... of interrupts A single combined interrupt comprising these four signals goes to the VIC SSPRXINTR SSP Receive FIFO Service Interrupt locally maskable SSPTXINTR SSP Transmit FIFO Service Interrupt locally maskable SSPRORINTR SSP Receive Overrun Interrupt locally maskable SSPRXTOINTR SSP Receive FIFO Timeout Interrupt All four interrupts are combined into a single interrupt SSPINTR The status of th...

Page 423: ...e FIFO is already full and an additional data frame is received causing an overrun of the FIFO Data is over written in the Shift Register but not the FIFO 14 1 6 4 Receive Timeout Interrupt SSPRXTOINTR is the Receive Timeout Interrupt This interrupt is asserted when the receive FIFO is not empty and the SSP has remained idle for a fixed 32 bit clock period it is not programmable This interrupt ens...

Page 424: ...eserved and must not be accessed Table 14 2 SSP Register Summary ADDRESS OFFSET NAME DESCRIPTION 0x000 CTRL0 Control Register 0 0x004 CTRL1 Control Register 1 0x008 DR Data Register 0x00C SR Status Register 0x010 CPSR Clock Prescale Register 0x014 IMSC Interrupt Mask Set and Clear Register 0x018 RIS Raw Interrupt Status Register 0x01C MIS Masked Interrupt Status Register 0x020 ICR Interrupt Clear ...

Page 425: ...e 15 8 CPD Clock Prescale Divisor To generate the bit rate and Serial Clock output SSPCLK pin the SSP uses two divisors on the generated 5 6448 MHz Clock Input when using the recommended 11 2896 MHz crystal This programmable clock rate divisor in the CTRL0 register A programmable prescaler in the Clock Prescaler register Divisor field SSPCLK is calculated as follows SSPCLK ƒCLOCK INPUT CPSR DVSR 1...

Page 426: ...0010 Undefined Operator 0011 4 bit data 0100 5 bit data 0101 6 bit data 0110 7 bit data 0111 8 bit data 1000 9 bit data 1001 10 bit data 1010 11 bit data 1011 12 bit data 1100 13 bit data 1101 14 bit data 1110 15 bit data 1111 16 bit data IMPORTANT This field resets to 0b0000 and must be programmed to a valid number prior to using the SSP Table 14 4 CTRL0 Fields BITS NAME DESCRIPTION ...

Page 427: ... slave systems it is possible for an SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line In such systems the RX lines from multiple slaves could be tied together To operate in such systems the SOD bit can be programmed to 1 1 SSP must not drive the SSPTX output in slave mode 0 SSP can drive the SSPTX output in sla...

Page 428: ...the receive buffer upper unused bits When the SSP is programmed for National Microwire frame format in master mode the default size for transmit data is eight bits the most significant byte is ignored The receive data size is controlled by software When the SSP is the slave device it will receive 8 bits of control data and transmit 4 to 16 bits of data The transmit FIFO and the receive FIFO are no...

Page 429: ... 0 0 0 0 0 1 1 RW W W W W W W W W W W W RO RO RO RO RO ADDR 0xFFFC6000 0x00C Table 14 10 SR Fields BITS NAME DESCRIPTION 31 16 Reserved Writing to these bits has no effect Reading returns 0 15 5 Reserved Write as zero Unpredictable behavior when read 4 BSY SSP Busy Flag 1 SSP is transmitting receiving a frame or the transmit FIFO is non empty 0 SSP is idle 3 REFI Receive FIFO Full 1 Receive FIFO i...

Page 430: ...DVSR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW WO WO WO WO WO WO WO WO RW RW RW RW RW RW RW RO ADDR 0xFFFC6000 0x010 Table 14 12 CPSR Fields BITS NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 8 Reserved Write as zero Unpredictable behavior when read 7 0 DVSR Clock Prescale Divisor To generate the bit rate and Serial Clock output SSPCLK the SSP uses two divisors on the g...

Page 431: ...FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TXIM RXIM RTIM RORIM RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW ADDR 0xFFFC6000 0x014 Table 14 14 IMSC Fields BITS NAME DESCRIPTION 31 4 Reserved Reading returns 0 Write the reset value 3 TXIM Transmit FIFO Inte...

Page 432: ...00 0x018 Table 14 16 RIS Fields BITS NAME DESCRIPTION 31 4 Reserved Reading returns 0 Write the reset value 3 TXRIS Transmit FIFO Raw Interrupt Status Gives the raw interrupt state pri or to masking of the Transmit FIFO interrupt 1 Interrupt asserted 0 Interrupt not asserted 2 RXRIS Receive FIFO Raw Interrupt Status Gives the raw interrupt state pri or to masking of the Receive FIFO interrupt 1 In...

Page 433: ...O RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFC6000 0x01C Table 14 18 MIS Fields BITS NAME DESCRIPTION 31 4 Reserved Reading returns 0 Write the reset value 3 TXMIS Transmit FIFO Masked Interrupt Status Gives the Transmit FIFO masked interrupt state 1 Interrupt asserted 0 Interrupt not asserted or is masked 2 RXMIS Receive FIFO Masked Interrupt Status Gives the Receive FIFO masked interrupt stat...

Page 434: ...9 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RTIC RORIC RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO WO ADDR 0xFFFC6000 0x020 Table 14 20 ICR Fields BITS NAME DESCRIPTION 31 2 Reserved Reading returns 0 Write the reset value 1 RTIC Receive Timeout in...

Page 435: ...MAE bit is set Table 14 21 DCR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TXDMAE RXDMAE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW ADDR 0xFFFC6000 0x024 Table 14 22 DCR Fields BITS NAME DESCRIP...

Page 436: ...ent all the Timer Capture Registers T1CAPn would repre sent all the Timer 1 Capture Registers T1CAPA is the specific register The timers are clocked by HCLK but scaled down internally for use in the PWM and com pare functions All counters are incremented by an internal prescaled counter clock or external clock and can generate an overflow interrupt when the counter increments from 0xFFFF to 0x0000...

Page 437: ...selected in step 2 the timer increments the counter of the corresponding timer on the third rising edge of HCLK after a rising edge by CTCLK The pulse length of CTCLK must be equal to or longer than two HCLK periods plus the setup and hold time see the Data Sheet for timing information Shorter pulses can cause incorrect counts If CTCLK is not in phase with HCLK inaccurate counts can occur Figure 1...

Page 438: ...tput Value Select the software must manually clear the compare output The CMPx hardware provides a highly accurate edge interrupt This output is not automatically set to the opposing value that is controlled through the pro gramming of the output value select bits within the CMP_CAP_CTRL register when the interrupt is cleared In this usage mode the host can clear the output compare signal by progr...

Page 439: ... PWM mode the signal is output on the CTCMPxA pin This mode uses a timer s two Timer Compare Registers TxCMPn to program the PWM period and duty cycle TxCMP1 programs the PWM period and TxCMP0 programs the PWM duty cycle The period must always be larger than the duty cycle Figure 15 5 illus trates this more clearly The value in TxCMP1 Register 1 is the period of the PWM The value in TxCMP0 Registe...

Page 440: ...pt a combined interrupt formed by the logical OR of the two compare two capture and one overflow interrupts in Timer 2 If an individual interrupt is enabled and the corresponding interrupt condition compare cap ture or overflow occurs a combined interrupt also occurs Once the interrupt condition occurs the combined Interrupt Output signal is asserted active to 1 It remains active until all compare...

Page 441: ...ister B 0x24 T0CAPC Timer 0 Capture Register C 0x28 T0CAPD Timer 0 Capture Register D 0x2C T0CAPE Timer 0 Capture Register E Table 15 2 Timer 1 Register Summary ADDRESS OFFSET NAME DESCRIPTION 0x30 CTRL1 Timer 1 Control Register 0x34 INTEN1 Timer 1 Interrupt Control Register 0x38 STATUS1 Timer 1 Status Register 0x3C CNT1 Timer 1 Counter Register 0x40 T1CMP0 Timer 1 Compare Register 0 0x44 T1CMP1 T...

Page 442: ... RW RW ADDR 0xFFFC4000 0x00 Table 15 5 CTRL0 Register Definitions BITS NAME DESCRIPTION 31 5 Reserved Reading this field returns 0 Write the reset value 4 2 SEL Timer 0 Clock Select Specifies the timer clock divisor The timer must be stopped with the CS bit before programming the divisor 000 HCLK 2 001 HCLK 4 010 HCLK 8 011 HCLK 16 100 HCLK 32 101 HCLK 64 110 HCLK 128 111 CTCLK 1 CS Start Stop Tim...

Page 443: ...this bit as well as other bits in this register Refer to Section 15 1 3 for a complete explanation 1 Output pin CTCMP0A is in PWM Mode 0 Output pin CTCMP0A is in Normal Mode and only uses the CMP0 Register 14 TC Timer 0 Counter Operation Programs Timer 0 as a free running counter or as an interval timer When 1 the counter clears upon matching the T0CMP1 Register Refer to Section 15 1 1 for a compl...

Page 444: ...the CTCAP0D pin This field and the capture function are inactive in PWM mode 00 Capture input CTCAP0D is ignored 01 Rising edge of CTCAP0D 10 Falling edge of CTCAP0D 11 Both edges of CTCAP0D 5 4 CAPC Input Edge Select Selects the edge used as the capture trigger on the CTCAP0C pin This field and the capture function are inactive in PWM mode 00 Capture input CTCAP0C is ignored 01 Rising edge of CTC...

Page 445: ...eration 1 Interrupt enabled for capture E 0 Interrupt disabled for capture E 6 CAPD_EN Timer 0 Interrupt Enable During Capture D Operation 1 Interrupt enabled for capture D 0 Interrupt disabled for capture D 5 CAPC_EN Timer 0 Interrupt Enable During Capture C Operation 1 Interrupt enabled for capture C 0 Interrupt disabled for capture C 4 CAPB_EN Timer 0 Interrupt Enable During Capture B Operation...

Page 446: ...1 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CAPE_ST CAPD_ST CAPC_ST CAPB_ST CAPA_ST CMP1_ST CMP0_ST OVF_ST RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW ADDR 0xFFFC4000 0x0C Table 15 11 STATUS0 Register Definitions BITS NAME DESCRIPTION 31 8...

Page 447: ...rite No effect 0 OVF_ST Timer 0 Overflow Status 1 Read Interrupt asserted Write Clear interrupt 0 Read No interrupt asserted Write No effect Table 15 12 CNT0 Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TM0CNT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 448: ...he CMP_CAP_CTRL register Table 15 14 T0CMPn Registers BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TM0CMP RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR CMP0 0xFFFC4000 0x14 CMP1 0xFFFC4000 0x18 Table 15...

Page 449: ...uring operation is selected with the CMP_CAP_CTRL Register Table 15 16 CAPn Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CAPTURE0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR CAPA 0xFFFC4000 0...

Page 450: ...ter Refer to Section 15 1 3 for a complete explanation and an example 0 Output CTCMP1A is normal and works only with the T0CMP1 Register 1 Output CTCMP1A is in PWM Mode 13 TC Timer 1 Operation This bit determines whether Timer 1 counter is to operate as either a free running counter or as an interval timer When 1 the counter clears upon matching CMP1 for Timer 1 This operation is only available wi...

Page 451: ...h edges of CTCAP1B 6 5 CAPA Input Edge Select Selects the rising edge falling edge both edges or ignores all changes of the input signal that is used as the capture trigger This field and the capture function are inactive in PWM mode 00 Capture input CTCAP1A is ignored 01 Rising edge of CTCAP1A 10 Falling edge of CTCAP1A 11 Both edges of CTCAP1A 4 2 SEL Count Clock Select Specifies the timer clock...

Page 452: ...x34 Table 15 21 INTEN1 Register Definitions BITS NAME DESCRIPTION 31 5 Reserved Reading this field returns 0 Write the reset value 4 CAPB_EN Timer 1 Interrupt Enable During Capture 1 Operation 1 Interrupt enabled for capture B 0 Interrupt disabled for capture B 3 CAPA_EN Timer 1 Interrupt Enable During Capture A Operation 1 Interrupt enabled for capture A 0 Interrupt disabled for capture A 2 CMP1_...

Page 453: ...21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CAPB_ST CAPA_ST CMP1_ST CMP0_ST OVF_ST RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW ADDR 0xFFFC4000 0x38 Table 15 23 STATUS1 Register Definitions BITS NAME DESCRIPTION 31 5 Reserved Reading this ...

Page 454: ...NT1 Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TM1CNT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC4000 0x3C Table 15 25 CNT1 Register Definitions BITS NAME DESCRIPTION 31 16 Reserved ...

Page 455: ...the CTRL1 register Table 15 26 T1CMPn Registers BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TM1CMP RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR T1CMP0 0xFFFC4000 0x40 T1CMP1 0xFFFC4000 0x44 Table 15 2...

Page 456: ...l used to trigger the capturing operation is determined by program ming the CTRL1 Register Table 15 28 T1CAPn Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CAPTURE1 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO ...

Page 457: ...s well as other bits in this register Refer to Section 15 1 3 for a complete explanation of this feature 0 Output CTCMP2A is normal and works only with the CMP2 Register 1 Output CTCMP2A is in PWM Mode 13 TC Timer 2 Counter Operation This bit determines whether the counter is to oper ate as a free running counter or interval counter When 1 the counter clears upon matching CMP1 for Timer 2 This ope...

Page 458: ...h edges of CTCAP2B 6 5 CAPA Input Edge Select Selects the rising edge falling edge both edges or ignores all changes of the input signal that is used as the capture trigger This field and the capture function are inactive in PWM mode 00 Capture input CTCAP2A is ignored 01 Rising edge of CTCAP2A 10 Falling edge of CTCAP2A 11 Both edges of CTCAP2A 4 2 SEL Count Clock Select Specifies the timer clock...

Page 459: ... 0x54 Table 15 33 INTEN2 Register Definitions BITS NAME DESCRIPTION 31 5 Reserved Reading this field returns 0 Write the reset value 4 CAPB_EN Timer 2 Interrupt Enable During Capture B Operation 1 Interrupt enabled for capture B 0 Interrupt disabled for capture B 3 CAPA_EN Timer 2 Interrupt Enable During Capture A Operation 1 Interrupt enabled for capture A 0 Interrupt disabled for capture A 2 CMP...

Page 460: ...25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CAPB_ST CAPA_ST CMP1_ST CMP0_ST OVF_ST RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW ADDR 0xFFFC4000 0x58 Table 15 35 STATUS2 Register Definitions BITS NAME DESCRIPTION 31 5 Reserved R...

Page 461: ...T2 Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TM2CNT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC4000 0x5C Table 15 37 CNT2 Register Definitions BITS NAME DESCRIPTION 31 16 Reserved R...

Page 462: ... the CTRL2 register Table 15 38 T2CMPn Registers BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TM2CMP RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR T2CMP0 0xFFFC4000 0x60 T2CMP1 0xFFFC4000 0x64 Table 15 ...

Page 463: ...al used to trigger the capturing operation is determined by program ming the CTRL Register Table 15 40 T2CAPn Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CAPTURE2 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO ...

Page 464: ...eceive FIFOs can be disabled to act like a one byte holding register Both FIFOs are 32 entries deep Programmable baud rate generator This enables division of the UART input clock by 16 to 65535 16 and generates an internal clock that is common to both transmit and receive portions of the UART The divisor can be a fractional number Interrupts The UART can issue an interrupt on transmit and receive ...

Page 465: ...protection These FIFO memories enable up to 32 entries to be stored independently in both transmit and receive modes All UART Control and Status Registers can be accessed through the APB Figure 16 1 UART0 UART1 and UART2 Block Diagram LH79525 63 APB INTERFACE AND REGISTER BLOCK BAUD RATE GENERATOR TRANSMITTER 32 12 RECEIVE FIFO BAUD16 RECEIVER INTERRUPT GENERATION DMA INTERFACE TRANSMIT FIFO STATU...

Page 466: ...it is sent until the time the next Start bit is received When the receiver receives an entire frame the UART transfers the received data and the frame status to the receive FIFO This buffer can have a depth of either 32 12 bit words FIFO Mode or one 12 bit word Character Mode as set with the UARTLCR_H FEN bit The Start bit works with the UART bit clock to synchronize the receiver with the source d...

Page 467: ... 1 for all programmed Stop bit periods following a data frame the UART sets the framing error status for that frame When Nine bit Mode is disabled enabling parity error detection causes the UART to compare the parity address received bit in each frame with the parity required for the hardware The UART sets the parity error address received status for each frame containing a parity error When Nine ...

Page 468: ... These elements must be transferred using programmed copying rather than DMA DMA requests are masked when the UART issues an error interrupt If the UART is in the Character Mode only the DMA Single Transfer Mode transferring one character per DMA operation can operate since only one character can be transferred to or from the FIFOs at any time As a result the programmed watermark level is not rele...

Page 469: ...er The nUARTRTS0 signal is reasserted when the receive FIFO has been emptied to less than the watermark level If RTS flow control is disabled and the UART is still enabled data is received until the receive FIFO is full or until no more data is transmitted to it 16 1 7 2 CTS Flow Control If CTS flow control is enabled the transmitter checks the nUARTCTS0 signal before trans mitting the next byte I...

Page 470: ...FFFC1000 the base address for UART2 is 0xFFFC2000 Table 16 2 shows the memory map for the UART registers Table 16 2 UART Register Summary ADDRESS OFFSET NAME DESCRIPTION 0x000 UARTDR Data Register 0x004 UARTRSR UARTECR Receive Status Register Read Error Clear Register Write 0x008 0x014 Reserved Do not access 0x018 UARTFR Flag Register 0x01C Reserved Do not access 0x020 UARTILPR IrDA Low Power Coun...

Page 471: ...rite the reset value 11 OE Receive FIFO Full Empty This bit indicates an overrun condition 1 Data is received and the receive FIFO is already full 0 There is an empty space in the FIFO and a new character can be written 10 BE Break Error This bit indicates a Break has occurred It is cleared to 0 after a Write to the UARTECR Register In FIFO Mode this error is associated with the character at the t...

Page 472: ... Bit Table REGISTER BIT MEANING UARTLCR_H 9BIT UARTDR PEAR 0 0 The parity of the received data character matches the parity selected as de fined by the EPS and SPS bits in the UARTLCR_H register In FIFO mode this error is associated with the character at the top of the FIFO 0 1 The parity of the received data character does not match the parity selected as defined by the EPS and SPS bits in the UA...

Page 473: ...UARTECR Register The FIFO contents remain valid since no further data is written when the FIFO is full only the contents of the shift register are overwritten The CPU must now read the data in order to empty the FIFO 2 BE Break Error In FIFO Mode this error is associated with the character at the top of the FIFO When a break occurs only one 0 character is loaded into the FIFO The next character is...

Page 474: ... 0 Transmit Holding Register not empty 6 RXFF Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register see Section 16 3 2 7 FIFO disabled This bit is set when the Receive Holding Register is full FIFO enabled RXFF bit is set when the receive FIFO is full 5 TXFF Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTL...

Page 475: ... value must produce a low power pulse duration of 1 41 μs 2 11 μs three times the period of SIR Baud Clock The minimum frequency of IrLPBaud16 ensures that pulses less than one period of UARTCLK are rejected as random noise but that pulses greater than two periods of UARTCLK are accepted as valid Table 16 13 describes the bit fields in the UARTILPR Register Table 16 12 UARTILPR Register BIT 31 30 ...

Page 476: ...8 7 6 5 4 3 2 1 0 FIELD BAUDDIVINT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR UART 0 0xFFFC0000 0x024 UART 1 0xFFFC1000 0x024 UART 2 0xFFFC2000 0x024 Table 16 15 UARTIBRD Fields BIT NAME DESCRIPTION 31 16 Reserved Reading returns 0 Write the reset value 15 0 BAUDDIVINT Integer Baud Rate Divisor This value is used with the Fractional Baud Rate Divi...

Page 477: ...responding Divisor Table 16 18 shows typical baud rates and their corresponding divisor using an example UART clock frequency of 11 2896 MHz Table 16 16 UARTFBRD Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD FRAC RESET 0 0 0 0 0 0 0 0 0 0 0 0...

Page 478: ...UART 0 0xFFFC0000 0x02C UART 1 0xFFFC1000 0x02C UART 2 0xFFFC2000 0x02C Table 16 20 UARTLCR_H Fields BIT NAME DESCRIPTION 31 10 Reserved Reading returns 0 Write the reset value 9 9BIT Nine bit Mode Enable Use this bit to enable Nine bit Mode 1 Nine bit Mode enabled characters are tagged during transmission as ad dress or data and checked during reception for address or data 0 Nine bit Mode disable...

Page 479: ...y See Table 16 21 1 PEN Parity Enable Bits 7 2 and 1 work together to set up the parity See Table 16 21 0 BRK SEND BREAK This bit commands the UART to enter a Break condition This bit must be asserted for at least one complete frame transmission time in order to generate a break condition The transmit FIFO contents remain unaffected during a break condition For normal use this bit must be cleared ...

Page 480: ... This bit enables CTS hard ware flow control Data is only transmitted when the nUARTCTS signal is as serted Only used with UART0 1 CTS hardware flow control enabled 0 CTS hardware flow control disabled 14 RTSEN RTS Hardware Flow Control Enable RTSEN This bit enables RTS hard ware flow control Data is only requested when there is space in the receive FIFO for it to be received Only used with UART0 ...

Page 481: ... transmitted as an active HIGH pulse with a width of 3 16th of the bit period When this bit field is set to 1 low level bits are transmitted with a shorter pulse width Enabling this bit lowers power consumption but may reduce the optical transmission distance 1 IrDA Low Power mode enabled 0 IrDA Low Power mode disabled 1 SIREN SIR Enable This bit can be programmed to enable or disable the SIR func...

Page 482: ...W RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RXIFLSEL TXIFLSEL RESET 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 RW RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW ADDR UART 0 0xFFFC0000 0x034 UART 1 0xFFFC1000 0x034 UART 2 0xFFFC2000 0x034 Table 16 25 UARTIFLS Fields BIT NAME DESCRIPTION 31 6 Reserved Reading returns 0 Write the reset value 5 3 RXIFLSEL Tr...

Page 483: ...IELD OEIM BEIM PEARIM FEIM RTIM TXIM RXIM CTS0IM RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RW RW RW RW RW RW RW RO RO RW RO ADDR UART 0 0xFFFC0000 0x038 UART 1 0xFFFC1000 0x038 UART 2 0xFFFC2000 0x038 Table 16 27 UARTIMSC Fields BITS NAME DESCRIPTION 31 11 Reserved Reading returns 0 Write the reset value 10 OEIM Overrun Error Interrupt Mask When read returns the current mask for the ...

Page 484: ...ble the TXI interrupt 0 Mask the TXI interrupt 4 RXIM Receive Interrupt Mask When read returns the current mask for the RXIM interrupt Write values 1 Enable the RXI interrupt 0 Mask the RXI interrupt 3 2 Reserved Reading returns 0 Write the reset value 1 CTS0IM CTS0 Interrupt Mask only for UART0 When Read returns the current mask for the CTS0 interrupt Write values 1 Enable the CTS0 interrupt 0 Ma...

Page 485: ... RO RO RO RO RO RO RO RO RO ADDR UART 0 0xFFFC0000 0x03C UART 1 0xFFFC1000 0x03C UART 2 0xFFFC2000 0x03C Table 16 29 UARTRIS Fields BITS NAME DESCRIPTION 31 11 Reserved Reading returns 0 Write the reset value 10 OERIS Overrun Error Interrupt Status Specifies the raw interrupt state of the UARTOEINTR interrupt 1 Interrupt pending 0 No interrupt 9 BERIS Break Interrupt Status Specifies the raw inter...

Page 486: ...S Receive Interrupt Status Specifies the raw interrupt state of the UARTRXINTR interrupt 1 Interrupt pending 0 No interrupt 3 2 Reserved Do not modify 1 CTS0IS CTS0 Interrupt Status only for UART0 Specifies the raw interrupt state of the UARTCTS0 interrupt 1 Interrupt pending 0 No interrupt 0 Reserved Reading returns 0 Write the reset value Table 16 29 UARTRIS Fields BITS NAME DESCRIPTION ...

Page 487: ... OEMIS Overrun Error Masked Interrupt Status Specifies the masked interrupt state of the UARTOEINTR interrupt 1 Interrupt pending 0 No interrupt or interrupt masked 9 BEMIS Break Error Masked Interrupt Status Specifies the masked interrupt state of the UARTBEINTR interrupt 1 Interrupt pending 0 No interrupt or interrupt masked 8 PEARMIS Parity Error Address Received Masked Interrupt Status Specifi...

Page 488: ... pending 0 No interrupt or interrupt masked 3 2 Reserved Reading returns 0 Write the reset value 1 CTS0MIS CTS0 Masked Interrupt Status only for UART0 Specifies the masked interrupt state of the CTS0 interrupt 1 Interrupt pending 0 No interrupt or interrupt masked 0 Reserved Reading returns 0 Write the reset value Table 16 31 UARTMIS Fields Cont d BIT NAME DESCRIPTION ...

Page 489: ...0x044 UART 1 0xFFFC1000 0x044 UART 2 0xFFFC2000 0x044 Table 16 33 UARTICR Fields BIT NAME DESCRIPTION 31 15 Reserved Reading returns 0 Write the reset value 10 OEIC Overrun Error Interrupt Clear 1 Clears the interrupt 0 No effect 9 BEIC Break Error Interrupt Clear 1 Clears the interrupt 0 No effect 8 PEARIC Parity Error Address Received Interrupt Clear 1 Clears the interrupt 0 No effect 7 FEIC Fra...

Page 490: ...17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD DMAOE TXDMAEN RXDMAEN RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW ADDR UART 0 0xFFFC0000 0x048 Table 16 35 DMACTRL Fields BIT NAME DESCRIPTION 15 3 Reserved Reading returns 0 Write the reset value 2 DMAOE D...

Page 491: ... a separate in and out FIFO except EP0 which shares a FIFO between IN and OUT The FIFOs allow DMA access Figure 17 1 shows the USB Device block diagram The individual blocks in the diagram are described in the subsequent sections 17 1 Theory of Operation The LH79524 and LH79525 implement a USB Device only All USB communications are managed by one or more external USB Hosts The USB Device is identi...

Page 492: ...5 to the Host Figure 17 2 USB Communication Endpoints LH79525 58 LH79525 USB DEVICE ENDPOINT 0 IN and OUT 32 BYTE SHARED FIFO ENDPOINT 1 IN and OUT 128 BYTE FIFO 2 ENDPOINT 2 IN and OUT ISO 1024 BYTE FIFO 2 ENDPOINT 3 IN 128 BYTE FIFO USB HOST CONTROL PIPE INTERRUPT PIPE DATA PIPE ISO DATA PIPE Table 17 1 Endpoint Function ENDPOINT TYPE FUNCTION EP0 IN OUT Control endpoint EP0 is always enabled wh...

Page 493: ...lic redundancy check CRC generation and checking Bit stuffing Endpoint address decoding for USB packets Interface signals for an external USB Transceiver The Serial Interface incorporates differential USB transceivers implementing a USB standard Full Speed interface allowing communication at up to 12 Mbits s 17 1 3 1 OUT_PKT_RDY Interrupt Operation for Endpoint 0 The USB Host via the protocol laye...

Page 494: ...the entire packet has been read or the DMA buffer becomes full It then releases the AHB and begins transfer ring the data just read to the selected FIFO This process is repeated until the entire packet has been read and loaded into the FIFO When the DMA controller is instructed to unload a packet it reads data from the selected FIFO into the DMA buffer until either the entire packet has been read ...

Page 495: ...ster CNTLx 0x0009 see Section 17 2 3 14 for the CNTLx register description The DMA Controller then requests bus mastership and transfers the packet to memory When it completes the transfer an interrupt is asserted to the VIC 5 Software must then program the OUTCSR1 OUT_PKT_RDY bit to 0 indicating that there is no packet waiting for transfer 17 1 5 2 DMA Mode 0 IN Endpoints For operation in DMA Mod...

Page 496: ...ice the DMA controller requests bus mastership and transfers the packet to memory The USB Device automatically clears the OUT_PKT_RDY bit in the appropriate OUTCSR1 register This process continues automat ically until the USB Device receives a short packet one of less than the maximum packet size for the endpoint signifying the end of the transfer This short packet will not be trans ferred by the ...

Page 497: ... to the USB Device The DMA controller then asserts an interrupt to the VIC If the last packet to be loaded was less than the maximum packet size for the endpoint the IN_PKT_RDY bit will not have be set Software must set the IN_PKT_RDY bit to allow the last short packet to be sent If the last packet to be loaded was of the maximum packet size software should still set the IN_PKT_RDY bit to send a n...

Page 498: ...not access 0x02C UIE Interrupt enable register for UIR 0x030 FRAME1 Frame number bits 0 to 7 0x034 FRAME2 Frame number bits 8 to 10 0x038 INDEX Index register for selecting the endpoint when accessing the status and control registers 0x03C Reserved Do not access 0x040 INMAXP Maximum packet size for IN endpoint INDEX register set to select Endpoints 1 2 or 3 only 0x044 CSR0 Control Status register ...

Page 499: ...its 0x20C COUNT1 DMA Channel 1 Byte Count 32 bits 0x210 Reserved Do not access 0x214 CNTL2 DMA Channel 2 Control 0x218 ADDR2 DMA Channel 2 AHB Memory Address 32 bits 0x21C COUNT2 DMA Channel 2 Byte Count 32 bits 0x220 Reserved Do not access 0x224 CNTL3 DMA Channel 3 Control 0x228 ADDR3 DMA Channel 3 AHB Memory Address 32 bits 0x22C COUNT3 DMA Channel 3 Byte Count 32 bits 0x230 Reserved Do not acce...

Page 500: ...O RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD ADDR_UPDATE FUNCTION_ADDR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW ADDR 0xFFFF5000 0x000 Table 17 5 FAR Fields BITS NAME FUNCTION 31 8 Reserved Reading returns 0 Write the reset value 7 ADDR_UPDATE Address Update Software must program this bit to 1 to inform the U...

Page 501: ...d before an SOF token a zero length data pack et is sent This bit is only used by endpoints performing Isochronous transfers 1 Wait for SOF token before sending the pending packet 0 Do not wait for the SOF token before sending packets 6 4 Reserved Reading returns 0 Write the reset value 3 USB_RESET USB RESET The USB block programs this bit to 1 when RESET signalling is received from the Host This ...

Page 502: ...r pending 0 Interrupt cleared or the above conditions are not met 2 EP2IN Endpoint2 IN Interrupt The EP2 interrupt is generated for Isochronous Interrupt IN transfers The USB block programs this bit to 1 when IN_PKT_RDY bit is cleared to 0 by the USB Host the FIFO is flushed by the USB Host and the USB Host has issued a STALL response IN token as indicated by SENT_STALL 1 Software clears this inte...

Page 503: ...0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFF5000 0x010 Table 17 11 OIR Fields BITS NAME FUNCTION 31 3 Reserved Reading returns 0 Write the reset value 2 EP2OUT EP2 Out Interrupt This interrupt is generated for Isochronous OUT trans fers The USB block programs this bit to 1 when OUT_PKT_RDY and SENT_STALL are set to 1 by the USB Host Software clears this interrupt by reading...

Page 504: ... block programs this bit to 1 when it receives RESET signalling from the USB Host Software clears this interrupt by reading this register 1 USB RESET Interrupt set 0 Interrupt cleared 1 RESINT RESUME Interrupt The USB block programs this bit to 1 when it receives RESUME signalling while in SUSPEND mode from the USB Host If the RESUME is due to a USB RESET the CPU is first interrupted with a RESUME...

Page 505: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD EP3INEN EP2INEN EP1INEN EP0INEN RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW ADDR 0xFFFF5000 0x01C Table 17 15 IIE Fields BITS NAME FUNCTION 31 4 Reserved Reading returns 0 Write the reset value 3 EP3INEN Endpoint 3 IN Interrupt Enable 1 Interrupt enabled 0 Interrupt disabled 2 EP2INEN Endpoint 2 IN Interrupt Enabl...

Page 506: ...RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD EP2OUTEN EP1OUTEN RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW ADDR 0xFFFF5000 0x024 Table 17 17 OIE Fields BITS NAME FUNCTION 31 3 Reserved Reading returns 0 Write the reset value 2 EP2OUTEN Endpoint 2 OUT Interrupt Enable 0 Interrupt disabled 1 Interrup...

Page 507: ...RW ADDR 0xFFFF5000 0x02C Table 17 19 UIE Fields BITS NAME FUNCTION 31 3 Reserved Reading returns 0 Write the reset value 3 SOFINTEN SOF Interrupt Enable 1 Interrupt enabled 0 Interrupt disabled 2 URINTEN USB RESET Interrupt Enable 1 Interrupt enabled 0 Interrupt disabled 1 RESINTEN RESUME Interrupt Enable 1 Interrupt enabled 0 Interrupt disabled 0 SUSINTEN SUSPEND Interrupt Enable Software program...

Page 508: ...0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFF5000 0x030 Table 17 21 FRAME2 Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD FRAME2 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ...

Page 509: ...s INCSR1 for Endpoint 3 first write 0x3 to the INDEX register then read or write INCSR1 17 2 3 1 Index Register INDEX The INDEX register determines which endpoint control status registers are accessed at address offsets 0x040 to 0x05C Table 17 24 INDEX Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO ...

Page 510: ...t see Universal Serial Bus Specification Revision 2 0 Chapter 9 A mismatch may cause unexpected results If a value greater than the IN FIFO see Table 17 2 size for the endpoint is written to this register the value will be automatically changed to the IN FIFO size If the value written to this register is less than or equal to half the IN FIFO size two IN packets can be buffered The register is res...

Page 511: ... 4 1 Clear the SETUP_END bit to 0 0 No effect 6 CLR_OUT Clear OUT_PKT_RDY Bit Software programs a 1 to this bit to clear OUT_PKT_RDY bit 1 1 Clear the OUTPACKETRDY bit to 0 0 No effect 5 SEND_STALL Send STALL Handshake Software writes a 1 to this bit at the same time it programs a 0 to OUT_PKT_RDY bit 0 when it decodes an in valid token The USB Host issues a STALL handshake to the current control ...

Page 512: ...Y IN Packet Ready Software programs this bit to 1 after writing a packet of data into ENDPOINT 0 FIFO The USB block programs this bit to 0 when the USB Host signals that the packet has been suc cessfully received at the Host An interrupt is generated when the USB Host clears this bit so software can load the next packet For a zero length data phase software programs IN_PKT_RDY and DATA_END bit 3 t...

Page 513: ...gine SIE toggles the Data PID sequence identifier for USB transactions with multiple data packets In the case of an error condition that requires the USB transaction to be re synchronized this bit must be programmed to 1 by software to reset the data toggle so that the SIE will transmit a DATA0 packet identifier on the succeeding transfer This bit is automatically cleared to 0 when the USB Device ...

Page 514: ...ing an IN token with the IN_PKT_RDY bit not set In Bulk Interrupt mode this bit is set 1 when a NAK is returned in response to an IN token 1 FIFO_NE FIFO Not Empty This bit indicates there is at least one data packet in the FIFO 1 Either 2 packets are in the IN FIFO and MAXP is equal to or less than half of the IN FIFO size or 1 packet is in the IN FIFO and MAXP is less than or equal to the IN FIF...

Page 515: ...ut intervention from software each time MAXP data is written If software writes less than MAXP data the IN_PKT_RDY bit must be programmed to 1 by software When two packets are in the IN FIFO IN_PKT_RDY will also be automatically set after the first packet has been sent if the second packet is the maximum packet size 0 Software must explicitly control the IN_PKT_RDY bit 6 ISO Isochronous Mode Enabl...

Page 516: ...ta represented by the value written to this register must not exceed the FIFO size for the OUT endpoint and should not exceed half the FIFO size if double buffering is required If a value greater than the OUT FIFO size see Table 17 2 for the endpoint is written to this register the value will be automatically changed to the OUT FIFO size If the value written to this register is less than or equal ...

Page 517: ...e Serial Interface Engine SIE tracks the Data PID sequence toggle received for USB transactions with multiple data packets An error condition that requires the USB transaction to be re synchronized this bit should be programmed to 1 to reset the data toggle so that the SIE expects a DATA0 packet iden tifier on the next transfer Software writes a 1 to this bit to clear the data toggle bit The USB b...

Page 518: ... No error 2 OVERRUN Data Overrun This bit indicates that an OUT packet cannot be loaded into the OUT FIFO The bit is only valid in isochronous mode 1 An OUT packet cannot be loaded into the OUT FIFO 0 No error 1 FIFO_FULL FIFO FULL This bit indicates no more packets can be accepted 1 2 packets are in the IN FIFO so the FIFO is full 0 FIFO is not full 0 OUT_PKT_RDY OUT Packet Ready The USB block pr...

Page 519: ...smaller than OUTMAXP software must manually clear OUT_PKT_RDY 1 OUT_PKT_RDY is automatically programmed to 0 without any intervention from software each time a complete packet is read from OUT FIFO 0 Software must explicitly clear the OUT_PKT_RDY bit after reading each packet 6 ISO Isochronous Enable Use this bit to enable the OUT endpoint for isochronous transfers or to enable the OUT endpoint fo...

Page 520: ...T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFF5000 0x058 with the INDEX register set to 0 Table 17 41 OUTCOUNT0 Fields BITS NAME FUNCTION 31 7 Reserved Reading returns 0 Write the reset value 6 0 OUTCOUNT0 Count of OUT EP0 Packet Bytes Number of bytes in the packet ready to be unloaded by software Table 17 42 OUTCOUNT1 Register BIT 31 30 29 28 27...

Page 521: ... 7 6 5 4 3 2 1 0 FIELD OUTCOUNT2 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFF5000 0x05C with the INDEX register set to 1 or 2 Table 17 45 OUTCOUNT2 Fields BITS NAME FUNCTION 31 3 Reserved Reading returns 0 Write the reset value 2 0 OUTCOUNT2 Count of OUT EP1 or EP2 Packet Bytes This contains the upper 3 bits of the number of bytes in the pa...

Page 522: ...O RO RO RO RO RO ADDR 0xFFFF5000 0x200 Table 17 49 INTR Fields BITS NAME FUNCTION 31 6 Reserved Reading returns 0 Write the reset value 5 INTR6 Channel 6 Interrupt Status 1 Interrupt pending from DMA Channel 6 0 No pending interrupt 4 INTR5 Channel 5 Interrupt Status 1 Interrupt pending from DMA Channel 5 0 No pending interrupt 3 INTR4 Channel 4 Interrupt Status 1 Interrupt pending from DMA Channe...

Page 523: ... Channel 5 0xFFFF5000 0x244 Channel 6 0xFFFF5000 0x254 Table 17 51 CNTLx Fields BITS NAME FUNCTION 31 16 Reserved Reading returns 0 Write the reset value 15 BUS_ERR Bus Error If a bus error occurs while DMA is accessing memory on the AHB the DMA controller immediately terminates the DMA transfer and interrupts the processor by setting this bit 1 Bus error occurred 0 No bus error 14 8 MAX Max Packe...

Page 524: ...RW RW ADDR Channel 1 0xFFFF5000 0x208 Channel 2 0xFFFF5000 0x218 Channel 3 0xFFFF5000 0x228 Channel 4 0xFFFF5000 0x238 Channel 5 0xFFFF5000 0x248 Channel 6 0xFFFF5000 0x258 Table 17 53 ADDRx Fields BITS NAME FUNCTION 31 0 ADDRx Memory Address for Channel x DMA Channel x AHB Memory Address Table 17 54 COUNTx Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD COUNT1 RESET 0 0 0 0 0 0...

Page 525: ...tored interrupt results in a low latency invocation of the service routine for that particular interrupt A default vectored interrupt requires the CPU to perform additional processing to determine which interrupt source caused the interrupt Any of the 32 lines can be assigned to any of the 16 interrupt vectors Any line not explicitly assigned to an interrupt vector is processed as a default vector...

Page 526: ...nterrupt 0 External General Purpose interrupt 8 External Interrupt 1 External General Purpose interrupt 9 External Interrupt 2 External General Purpose interrupt 10 External Interrupt 3 External General Purpose interrupt 11 External Interrupt 4 External General Purpose interrupt 12 External Interrupt 5 External General Purpose interrupt 13 External Interrupt 6 External General Purpose interrupt 14...

Page 527: ...xample to assign the Real Time Clock Alarm interrupt interrupt 15 to address 0x12345678 using vector 10 program the VECTADDR10 register to address 0x12345678 the location of the ISR for the RTC Alarm then program VECTCTRL10 to 0x0000000F RTC Alarm interrupt number 15 Then program the VECTCTRL10 E bit to 1 to enable the vector After all interrupt vector addresses and associations have been programm...

Page 528: ...l interrupt can still be asserted causing the VIC to enter the ISR a second time Because the VIC samples the line after the clear it generates another interrupt to the ARM core if the line is recognized to be still active To avoid this situation clear the source of the interrupt as early as practical in the ISR Doing so ensures a maximum delay between clearing the external interrupt and clearing t...

Page 529: ...ECTADDR0 Vector Address 0 Register 0x104 VECTADDR1 Vector Address 1 Register 0x108 VECTADDR2 Vector Address 2 Register 0x10C VECTADDR3 Vector Address 3 Register 0x110 VECTADDR4 Vector Address 4 Register 0x114 VECTADDR5 Vector Address 5 Register 0x118 VECTADD6 Vector Address 6 Register 0x11C VECTADDR7 Vector Address 7 Register 0x120 VECTADDR8 Vector Address 8 Register 0x124 VECTADDR9 Vector Address...

Page 530: ...x238 VECTCTRL14 Vector Control 14 Register 0x23C VECTCTRL15 Vector Control 15 Register 0x240 0x308 Reserved Do not access 0x30C ITOP Interrupt Test Output Register 0x310 Reserved Do not access Table 18 2 VIC Register Summary Cont d ADDRESS OFFSET NAME DESCRIPTION Table 18 3 IRQSTATUS Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD IRQStatus RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 531: ...O RO RO RO ADDR 0xFFFFF000 0x004 Table 18 6 FIQSTATUS Fields BITS NAME DESCRIPTION 31 0 FIQStatus Interrupt Status After Masking Shows the status of the interrupts after masking by the IntEnable and IntSelect Registers For each bit 1 Interrupt is active and generates an FIQ exception to the ARM7 core 0 Interrupt is not active Table 18 7 RAWINTR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 1...

Page 532: ... 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFFF000 0x00C Table 18 10 INTSELECT Fields BITS NAME DESCRIPTION 31 0 IntSelect Interrupt Type Selects the type of interrupt for the interrupt request For each bit 1 FIQ interrupt 0 IRQ interrupt Table 18 11 INTENABLE Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD IntEnable RESET 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 533: ... 21 20 19 18 17 16 FIELD IntEnable Clear RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD IntEnable Clear RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO ADDR 0xFFFFF000 0x014 Table 18 14 INTENCLEAR Fields BITS NAME DESCRIPTION 31 0 IntEnable Clear Clear IntEnable Bit Cl...

Page 534: ...example as software interrupt can be generated for interrupt number 0 to test the interrupt processing of the hardware WDT interrupt Table 18 15 SOFTINT Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD SoftInt RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD SoftInt RESET 0 0 0 0 0 0 0 0 0 0 0...

Page 535: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD SoftInt Clear RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD SoftInt Clear RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO ADDR 0xFFFFF000 0x01C Table 18 18 SOFTINTCLEAR FIelds BITS NAME DESCRIPTION 31 0 SoftInt Clear Cle...

Page 536: ... VECTADDR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD VectorAddr RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD VectorAddr RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFFF000 0x030 Table 18 20 VECTADDR Fields BITS NAME DESCRIPTION 31 ...

Page 537: ...12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD VICVectorAddr RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR VECTADDR0 0xFFFFF000 0x100 VECTADDR1 0xFFFFF000 0x104 VECTADDR2 0xFFFFF000 0x108 VECTADDR3 0xFFFFF000 0x10C VECTADDR4 0xFFFFF000 0x110 VECTADDR5 0xFFFFF000 0x114 VECTADDR6 0XFFFFF000 0x118 VECTADDR7 0xFFFFF000 0x11C VECTADDR8 0xFFFFF000 0x120 VECTADDR9 0xFF...

Page 538: ...8 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD E IntSource RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW ADDR VECTCTRL0 0xFFFFF000 0x200 VECTCTRL1 0xFFFFF000 0x204 VECTCTRL2 0xFFFFF000 0x208 VECTCTRL3 0xFFFFF000 0x20C VECTCTRL4 0xFFFFF000 0x210 VECTCTRL...

Page 539: ...RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD VF VI RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFFF000 0x30C Table 18 28 ITOP Fields BIT NAME DESCRIPTION 31 8 Reserved Reading returns 0 Write the reset value 7 VI VIC IRQ Output Status 1 an IRQ interrupt request to the ARM core is asserted 0 an IRQ interrupt request to the...

Page 540: ...lue on each HCLK cycle Upon underflow timing out the WDT causes either A flag to be set in the Reset Clock and Power Controller RESETSTATUS WDTO triggering a system reset or An interrupt is sent to the Vectored Interrupt Controller VIC Note that the interrupt is only recognized in the Active Mode Three conditions cause the TOP value to be loaded into the counter After a system reset After a counte...

Page 541: ...on 1 0 Figure 19 1 Watchdog Timer Block Diagram LH79525 38 RESET CLOCK GENERATION AND POWER CONTROL RCPC VECTORED INTERRUPT CONTROLLER VIC WATCHDOG TIMER WDT WDT TIMEOUT RESET PCLK nWDINT ADVANCED PERIPHERAL BUS APB ADVANCED HIGH PERFORMANCE BUS AHB 32 32 ...

Page 542: ...h 0 of the current value When all of COUNT 3 0 are 0 the WDT has timed out Software can set WDT operation to cause a system reset or an interrupt followed by a system reset To cause a system reset after one WDT timeout program the CTL Interrupt First bit CTL IF to 0 To generate an interrupt after one WDT timeout and a reset only if the interrupt is not serviced program CTL IF to 1 The first timeou...

Page 543: ...ffsets in Table 19 1 are relative to the Timer base address 0xFFFC3000 Table 19 1 Watchdog Timer Memory Map ADDRESS OFFSET NAME DESCRIPTION 0x00 CTL Watchdog Control Register 0x04 RST Watchdog Counter Reset 0x08 STATUS Watchdog Status Register 0x0C COUNT0 Current Count bits 7 0 0x10 COUNT1 Current Count bits 15 8 0x14 COUNT2 Current Count bits 23 16 0x18 COUNT3 Current Count bits 31 24 ...

Page 544: ... the new value takes effect after a counter reset command or after the count reaches 0 3 FRZ Freeze Set this bit while the watchdog is enabled to prevent clearing EN Only a System Reset can clear FRZ 1 When WDT is enabled the EN bit is frozen and cannot be cleared set to 0 0 WDT function is not frozen FRZ cannot be cleared by writing a 0 to this bit a 0 is only valid when this bit is read FRZ is o...

Page 545: ... 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RST RESET undefined TYPE WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO ADDR 0xFFFE3000 0x04 Table 19 5 RST Field BIT NAME DESCRIPTION 31 16 Reserved Reading this field returns 0 Write the reset value 15 0 RST Reset Write 0x1984 to this register to reset the WDT and commence counting down If ...

Page 546: ...O RO RO RO RO RO RO RO RO RO RO RO ADDR 0xFFFE3000 0x08 Table 19 7 STATUS Fields BIT NAME DESCRIPTION 31 8 Reserved Reading this field returns 0 Write the reset value 7 INT INT This bit reports the WDT timeout interrupt status 1 An interrupt has occurred and has been sent to the VIC 0 No interrupt has occurred 6 Reserved Reading this bit returns 1 Write the reset value 5 Reserved Reading this bit ...

Page 547: ...e 0x00 the WDT has timed out Table 19 8 COUNTx Description BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD COUNT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ADDR COUNT0 0xFFFE3000 0x0C COUNT1 0xFFFE3000 0...

Page 548: ... a separate timing ASIC AMBA Advanced Microprocessor Bus Architecture This architecture is an open standard for an on chip bus connecting the blocks of an SoC APB Advanced Peripheral Bus Defined in the AMBA specification the APB connects the lower performance peripheral blocks In the LH79524 LH79525 the APB connects a number of peripherals that do not require the speed or bandwidth of the AHB The ...

Page 549: ... of a packet together and throwing away the carry The same as done at the receiving end If the checksums are different a transmission error occurred Generally the receiver asks the transmitter to resend the pre vious data packet Chip A packaged integrated circuit device CLCDC The on chip Color Liquid Crystal Display Controller Core See ARM720T Core CPSR Current Program Status Register In ARM archi...

Page 550: ...ng access to all external memory devices and the embedded SRAM frame buffer ENDEC Encoder and Decoder Endianness Describes the bit byte or word sequence of data communication or storage associating the most significant or least significant end of a data sequence with the lowest address or with the beginning of reception or transmission See Big endian and Little endian Endpoint Address The combinat...

Page 551: ...es a Vectored Interrupt Controller VIC IRQ Interrupt Request The hardware responds to an IRQ by saving some registers and moving execution to the address provided by the VIC for interrupt handling software IRQ interrupts are lower priority than FIQ See FIQ Isochronous Data A continuous stream of data delivered at a steady rate IrDA A serial half duplex optical communications protocol sponsored by ...

Page 552: ...Independent Interface Media Independent Interface Standard developed for Fast Ethernet in IEEE 802 3u specification The Fast Ethernet equivalent to the AUI in 10 Mbits s Ethernet allowing different types of Fast Ethernet media to be connected to a Fast Ethernet device via a common interface MMC MultiMediaCard The complete specification is available at the MultiMediaCard Associa tion website http w...

Page 553: ...rk management tool to gather information at a single point RTC Real Time Clock RW Read or Write RW bits or fields can be read from or written to SIR Serial InfraRed SoC System on Chip A single chip microprocessor system directly supporting peripherals used by an embedded design product SOF Start of Frame The beginning of a USB defined frame SOF is the first transaction in each frame The SOF allows...

Page 554: ...cal group of devices defined by software VLANs allow network administrators to resegment their networks without physically rearranging the devices or network connections Workstations on different LANs can be connected using VLAN tagging where tags are assigned to the frames transmitted by devices Volatile Memory A general term for any memory technology that loses its contents when power is removed...

Page 555: ...E Ltd 438A Alexandra Road 05 01 02 Alexandra Technopark Singapore 119967 Phone 65 271 3566 Fax 65 271 3855 SHARP Electronic Components Korea Corporation RM 501 Geosung B D 541 Dohwa dong Mapo ku Seoul 121 701 Korea Phone 82 2 711 5813 8 Fax 82 2 711 5819 CHINA HONG KONG SHARP Microelectronics of China Shanghai Co Ltd 28 Xin Jin Qiao Road King Tower 16F Pudong Shanghai 201206 P R China Phone 86 21 ...

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