COMe-cEL6 - User Guide, Rev.1.3
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Sub-screen
Next Level Sub-screens / Description
PCH/IO
Configuration>
(continued)
TSN GBE
Configuration>
(continued)
PSE TSN GBE 0 Link
Speed>
PSE TSN GBE 0 link speed configuration.
[RefClk 38.4MHz 2.5Gbps, RefClk 38.4MHz 1Gbps]
Flex IO Lane
Assignment>
Read only field
[Lane 7]
Sub-screen
Next Level Sub-screens / Description
PCH/IO
Configuration>
PCH Master
Clock Gating
Control>
[Disabled, Default]
PCH Master
Power Gating
Control>
[Disabled, Default]
State After G3>
State to go to when power is re-applied after a power failure (G3 State)
[S0 state, S5 State]
Port 80h
Redirection>
[LPC Bus, PCIE Bus]
Enhance Port
80h LPC
Decoding>
Support the word/dwor decoding of port 80h behind LPC
[Enabled, Disabled]
Legacy IO Low
Latency>
Set the enable low latency of legacy OP. Some systems require lower Io
latency irrespective of power. This is a tradeoff between power and IO
latency. [Enabled, Disabled]
PCH Energy
Reporting>
Enable energy Report. MUST set as ENABLED. This is only for test purposes.
[Enabled, Disabled]
LPM S0i2.0>
Enables or disables the SOix sub-states. This setting is for test purpose.
SOix sub-states should be enables for production.
[Enabled, Disabled]
LPM S0i2.1>
LPM S0i2.2>
LPM S0i3.0>
LPM S0i3.1>
LPM S0i3.2>
LPM S0i3.3>
LPM S0i3.4>
IEH Mode>
Enable or Bypass IEH Mode [Bypass, Enabled]
Enable TCO
Timer>
When disables, it disables PCH ACPI timer, stops TCO timer abs ACPI WDAT
table will not be published.
[Enabled, Disabled]
PCIe PLL SSC>
PCIe PLL SSC percentage
Auto: Keep HW default, no BIOS override (range 0.0% to 2.0%)
[Auto, 0.9%, 0.1%, 0.2%, …. 2.0%, Disabled]
Flash Protection
Range Register>
Enables the flash protection range registers (FRPP)
[Enabled, Disabled]
LGMR>
64 KB memory block for LGMR (LPC Memory Range Decode)
[Enabled, Disabled]