COMe-cEL6 - User Guide, Rev.1.3
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Sub-screen
Next Level Sub-screens / Description
PCH-IO
Configuration>
(continued)
PCI Express
Configuration>
(continued)
PCIE Express
Root Port
[1 to 4]>
(continued)
PCH PCIe LTR Configuration
LTR>
PCIe latency reporting
[Enabled, Disabled]
Snoop Latency
Override>
Disabled- disable override
Manual- Manually enter override
values
Auto- maintain default BIOS flow
[Disabled, Manual, Auto]
Non Snoop
Latency Override>
Disabled- disable override
Manual- Manually enter override
values
Auto- maintain default BIOS flow
[Disabled, Manual, Auto]
Force LTR
Override>
Enabled: LTR override values forced
and LTR messages from the device
ignored
Disabled: LTR override values are
not forced
[Enabled, Disabled]
LTR Lock>
PCIe LTR configuration lock
[Enabled, Disabled]
Extra Options>
Detect Non-
Compliance
Device>
When enable will
take more post time
[Enabled, Disabled]
Prefetch
Memory>
Prefetchable
memory range for
this root bridge [10]
Reserved
Memory
Alignment>
Range (0 to 31 bits)
[1]
Prefetchable
Memory
Alignment>
Range (0 to 31 bits)
[1]
PCI Clock>
Clock
0
Assignment>
Platform-POR : clock assigned to
PCIe port or LAN according to module
layout
Enable- keep clock even if unused
Disable- disable clock
[Platform-POR, Enabled, Disabled]
ClkReq for Clock0>
Platform-POR : CLKREQ signal
assigned to CLKSRC according to
module layout
Disable- disable clock
[Platform-POR, Disabled]
