© SAMSUNG Electronics Co., Ltd.
6
/TA (/DTACK) Signal Control
Among components controlled by the CPU, some cannot keep up with the CPU because of
their slow processing speed. Those components require additional time for processing
commands. The OfficeServ 12 system uses the /TA port of MPC 855T to make the CPU
wait for the additional time needed. This port usually maintains low status, which allows
the CPU to operate without any interruptions. When controlling a component having slow
processing speed, the port changes the signal to high status.
The CPU then recognizes the change and maintains the command execution status until the
/TA signal returns to normal status.
OfficeServ 12 uses DTACK signals generated from the engine, DSP(Digital Signal
Processor), MGI, and 2BRI boards.
Figure 4.4 /TA (/DTACK) Signal Control
CPU (MPC 855T) Interrupt
The CPU(MPC 855T) has an eight-level interrupt architecture. The priority of each level is
determined by the level entering the /IPL0, /IPL1, and /IPL2 ports. Level 7 indicates the
highest priority and level 1 indicates the lowest priority. Level 0 indicates that no interrupt
is requested.
•
IRQ0(Level7): /NMI: Watchdog
•
IRQ1(Level6): /INTS_DMC: DLI
•
IRQ2(Level5): ./INTISAC0: BRI
/INTISAC1: BRI
•
IRQ3(Level4): .Interrupt within CPU
•
IRQ4(Level3): /INT_QSLAC1: SLI
/INT_QSLAC2: SLI
/HINT: MGI
/TA
DT_DBD
DT_DSP
DT_MGI
STC9604
Wired OR
Summary of Contents for OfficeServ 12
Page 1: ...GANA 000029 Ed 001 OfficeServ 12 Service Manual ...
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