Samsung MSYS 5150, Service Manual

Page: 68 / 210

S I G N A L PIN No. Type Description
RTS 64 I Request to send
When the RTS input is forced low, the transmitter starts transmitting the
modem training sequence has been transmitted (signaled by the CTS pin
and CTSB bit becoming active), data present at either the TXDI input pin
in serial mode (PDME bit is reset) or written into the DBFR register in
parallel mode (PDME bit is set) is modulated and transmitted. The RTS
input pin is logically ORed with the RTSB bit in the interface memory.
CTS 78 O Clear to send
CTS is used to indicate of that the transmission training sequence has
been completed and the modem is ready to transmit any data present at
either the TXID input pin in serial mode (PDME bit is reset) or in DBFR
in parallel mode (PDME bit is set).
RLSD 79 O Received line signal detector
RLSD becomes active at the end of the reception of the training sequence
indicating the beginning of data reception. If no training is detected but
the received energy level is above the RLSD off-to-on threshold, RLSD
will become active.
X TALI 68 I Oscillator In/Out
X TALO 69 O An external 24.00014MHz (KS16116) or 38.00053 MHz (KS16117) crystal
and two capacitors are connected to the XTALI and XTALO.
Alternatively, an external crystal oscillator of the appropriate frequency
can be connected to the XTALI input leaving XTALO unconnected.
In order to minimize electromagnetic emissions and ensure proper
oscillator start up and operation, the crystal and the capacitors should be
placed as close as possible to the XTALI and XTALO pins. Further, the
circuit board traces connecting the crystal and capacitors to XTALI and
X TALO should be as short as possible. The use of circuit board bias
should be avoided in the crystal oscillator circuitry and circuit board
traces should be routed using curved turns.
PORI 67 I Power On reset In
When power is first applied to the modem, PORI is held low for
approximately 350ms. The modem is turn ready for normal operation
15ms after the low to high transition of PORI.
V
D D
22, 72 Power +5V Digital voltage supply
This pin nust be connected to +5V 5% supply. The +5V Digital power
supply voltage ripple should not exceed 100mV
p-p.
V
cc
46 Power +5V Analog voltage supply
This pin nust be connected to +5V 5% supply. The +5V Analog power
supply voltage ripple should not exceed 100mV
p-p.
G N D D 6, 7, 16, G N D Digital ground
23, 50, 66, These pins must be connected to digital ground.
77, 80, 81,
89, 92, 97
G N D A 17, 21, G N D Analog ground
30, 43, 47 These pins must be connected to analog ground.
Table 2-1 Hardware Interface Signal Descriptions (Cont.)
5-20 Samsung Electronics
Circuit Description