Samsung MSYS 5150, Service Manual

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Table 1-1 KS32C6100 Signal Descriptions (Cont.)
S I G N A L PIN No. Type Description
nWE[3:0]/ 33~36 O Not data write enable for SRAM/External IO. Whenever a memory
ExtMnDB[3:0] access for SRAM/External IO occurs, the four nWE outputs indicate
the byte selections and control the write enable port of the specific
devices.
In external bus master mode, it acts as ExtMnDB[3:0] to indicate the
byte latch for external master accessing memory.
DA[12:0] 128~133 I/O DA[12:0] acts as an output for the 13-bit DRAM address bus. In
/ 135~141 external master mode, it acts as an input, in which ExtMA[27:24]
corresponds to the higher 4 bits out of 28-bit external master address
ExtMA[27:24] 128~131 bus ExtMA[27:0]; ExtMBST is burst mode selection signal; ExtMRnW
ExtMBST 138 is R/W control signal; and ExtMAS[1:0] is memory access size control
ExtMAS[1:0] 139~140 signal which is used to inform KS32C6100’s memory controller
ExtMRnW 141 that the external master will access memory in byte (00), halfword (10).
Note the state (11) for ExtMAS [1:0] is not used.
nRAS[5:0] 122~127 O Not row address strobes for DRAM banks. The KS32C6100 supports
up to six DRAM banks. One nRAS output is provided for each bank.
nCAS[3:0] 116~118 O Not column address strobes for DRAM. The four nCAS outputs
121 indicate the byte selections whenever a DRAM bank is accessed.
n D O E 115 O Not output enable for DRAM. Whenever a DRAM access occurs,
the nOE output controls the output enable port of the specific DRAM.
n D W E 114 O Not write enable for DRAM. Whenever a DRAM access occurs, the
nWE output controls the write enable port of the specific DRAM.
nSRD[1:0] 144, 146 O Not special I/O read strobe with address latch.
nSWR[1:0] 145, 147 O Not special I/O write strobe with address latch.
ExtMREQ 23 I External master request. The ExtMREQ input signal indicates that
the external master requests to hold KS32C6100 system bus.
ExtMACK 24 O Acknowledge for external master holding request. This output signal
indicates that the external master holding request has been accepted.
ExtMnDL 25 I/O External master data latch signal.
U C L K 156 I The external UART clock source input. Usually, MCLK is used as the
U A RT clock source.
R X D 151 I Receive data input for the UART. RXD is the UART’s input signal for
receiving serial data.
D T R 149 I Data terminal ready. DTR input signals the KS32C6100 that the
peripheral (or host) is ready to transmit or receive serial data.
T X D 150 O Transmit data output for the UART. TXD is the UART’s output for
transmitting serial data.
D S R 148 O Data set ready. DSR output signals the host (peripheral) that the
KS32C6100 UART is ready to transmit or receive serial data.
Samsung Electronics 5-11
Circuit Description